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432 Commits 5 Branches 14 Tags 5.7 MiB
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432 Commits

Author SHA1 Message Date
Florent Kermarrec 050670829a core/controller: remove simulation workaround 2018-08-29 16:48:06 +02:00
Florent Kermarrec bc8a9cef7d README: update 2018-08-29 16:34:53 +02:00
Florent Kermarrec 6f7ae8496b frontend/axi: increase default depth of buffers to improve performance 2018-08-29 16:28:07 +02:00
Florent Kermarrec ed7eef12d4 phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) 2018-08-29 14:15:31 +02:00
Florent Kermarrec c37d3af5b5 frontend/bist: only keep random datas (we can generate random addresses with control) 2018-08-28 22:54:23 +02:00
Florent Kermarrec b1e734b2ac frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) 2018-08-28 18:59:56 +02:00
Florent Kermarrec 92c8513598 frontend/axi: add buffer to accept command before converting burst to beats 2018-08-28 14:09:59 +02:00
Florent Kermarrec c15c47497a test/test_axi: split reads/writes generators 2018-08-28 14:09:12 +02:00
Florent Kermarrec 95cb7cdba5 test: rename read/write generators to handlers 2018-08-28 13:40:50 +02:00
Florent Kermarrec d5d673708d frontend/axi: fix read id 2018-08-28 13:39:29 +02:00
Florent Kermarrec 10229d1e7d test/test_axi: improve test_axi2native 2018-08-28 13:39:11 +02:00
Florent Kermarrec 295f016fd2 frontend/axi: add features/limitations 2018-08-28 12:39:49 +02:00
Florent Kermarrec 6a46ea3052 test/test_bist: add generator test, remove async test 2018-08-28 11:50:11 +02:00
Florent Kermarrec 7677a853f1 core/bankmachine: expose cmd_buffer_buffered param and small cleanup 2018-08-28 11:19:48 +02:00
Florent Kermarrec 7a5ac75e22 test/test_axi: improve test_axi2native 2018-08-27 18:39:36 +02:00
Florent Kermarrec d53832d55a frontend/axi: split LiteDRAMAXI2Native (write path and read path) 2018-08-27 18:39:09 +02:00
Florent Kermarrec c846b8b1c7 frontend/axi: add burst support (fixed/incr) 2018-08-27 16:21:12 +02:00
Florent Kermarrec 3fa77c8417 phy/s6ddrphy: use cwl only for DDR3 2018-08-27 14:06:32 +02:00
Florent Kermarrec d9b5bb7247 frontend/bist: support axi with addressing in bytes 2018-08-27 12:42:30 +02:00
Florent Kermarrec 137061734b frontend/axi: addressing in bytes not internal dwords 2018-08-27 11:05:37 +02:00
Florent Kermarrec 06f841dc2a sdram_init: compute write recovery cycles (we were using max value) 
Also replace sdram_phy_settings with phy_settings
 2018-08-22 14:44:46 +02:00
Florent Kermarrec 53c75f50c8 phy/s7ddrphy: add dqs preamble/postamble 2018-08-22 12:32:19 +02:00
Florent Kermarrec 1c083ea9df sdram_init: split init_sequence generation and header geneneration and add .py header genration 2018-08-21 18:14:19 +02:00
Florent Kermarrec d7d60cf30b Merge branch 'master' of http://github.com/enjoy-digital/litedram 2018-08-21 15:58:30 +02:00
Florent Kermarrec ae6f10a7e1 sdram_init: use 60ohm as rtt_wr default value 
Seems the best for point to point according to tn4113_ddr3_point_to_point_design
 2018-08-21 15:58:07 +02:00
enjoy-digital cd330b4b44
Merge pull request #28 from AlphamaxMedia/refactor-master 
i think there's a missing "self" in the params
 2018-08-21 15:22:50 +02:00
Florent Kermarrec 522cbc97a1 frontend: add AXI support for dma and bist 2018-08-21 14:49:10 +02:00
Florent Kermarrec 57157345cf frontend: add initial AXI support 2018-08-21 13:39:46 +02:00
Florent Kermarrec 97349bc11b frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native 2018-08-21 13:27:49 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
bunnie 818c6785f0 update module settings to reflect latest changes 2018-08-21 17:59:54 +08:00
bunnie c9b8db5dc9 i think there's a missing "self" in the params 2018-08-21 17:28:42 +08:00
Florent Kermarrec 0b6e21ab6d improve ddr3 electrical settings 2018-08-21 10:45:42 +02:00
bunnie 697eaafc4c add board tuning parameters 2018-08-21 09:20:21 +02:00
Florent Kermarrec 9a57c4e88c phy/s7ddrphy: add DDR3-800 timings 2018-08-21 09:02:57 +02:00
Florent Kermarrec 9401b92c71 move sdram_init to litedram 2018-08-20 15:37:39 +02:00
Florent Kermarrec 209dc0d781 frontend/bist: add dynamic random data and addressing 2018-08-17 13:49:27 +02:00
Florent Kermarrec b13962c7bd core/multiplexer: fix 1:1 2018-08-16 15:48:26 +02:00
Florent Kermarrec a215ac7d8b core/multiplexer: fix count signal width (when max<2) 2018-08-16 15:33:03 +02:00
Florent Kermarrec ad8438f5d3 core/controller: enable auto_precharge by default 2018-08-15 17:04:16 +02:00
Florent Kermarrec bba491396f core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge 2018-08-15 17:03:06 +02:00
Florent Kermarrec 2e362ee160 core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) 2018-08-15 16:13:39 +02:00
Florent Kermarrec 6d234219b4 core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead 2018-08-15 13:30:06 +02:00
Florent Kermarrec 23358b5d29 core/multiplexer: use self.submodules for timing controllers, fix tFAW count 2018-08-15 13:04:19 +02:00
enjoy-digital db4ec67741
Merge pull request #24 from JohnSully/AutoPrecharge 
Auto precharge
 2018-08-15 12:46:29 +02:00
627cccde59 Fix tCCD timing which watched the wrong command 2018-08-14 23:55:01 -04:00
16a852bda5 Revert "core/refresher: synchronize valid" 
This reverts commit 6620a91a22 because it fails to issue a refresh command
 2018-08-14 23:23:24 -04:00
a4be642d56 Fix multiple timings ignored 2018-08-14 22:42:02 -04:00
771ccfdc41 Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge 2018-08-14 15:25:21 -04:00
Florent Kermarrec 6620a91a22 core/refresher: synchronize valid 2018-08-14 15:30:24 +02:00