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449 Commits 5 Branches 14 Tags 5.7 MiB
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73 Commits

Author SHA1 Message Date
Florent Kermarrec d6350d9fec test/test_axi: reduce rand_level on writes 2018-12-05 11:44:38 +01:00
Florent Kermarrec 6778c72665 test/test_axi: cleanup, all tests passings. 2018-12-03 08:01:33 +01:00
Florent Kermarrec 7f5d749c6b test: add missing +x 2018-11-30 11:58:45 +01:00
Florent Kermarrec 7ef4869db9 test/test_axi: also add randomness on rdata.valid and wdata.ready 2018-11-30 11:22:04 +01:00
Florent Kermarrec 3db68cdd50 test/test_axi/axi2native: add tests for each randomness parameters (ease finding regressions issues) 2018-11-30 10:40:45 +01:00
Florent Kermarrec 190b1bd01f test/test_axi/axi2native: add finer control on randomness 2018-11-30 09:40:13 +01:00
Florent Kermarrec 4f137b9334 test/test_axi/axi2native: add random on len, just use writes as reads 2018-11-29 23:45:38 +01:00
Florent Kermarrec 2a799e4f1d test/test_axi: set size on axi2native test 2018-11-29 23:45:31 +01:00
Florent Kermarrec 93e8510f55 test/test_axi: add bursts to axi2native 2018-11-12 18:00:28 +01:00
Florent Kermarrec e27fbc2430 test/test_axi: move definitions to top and make Access herit from Burst 2018-11-12 13:09:05 +01:00
Florent Kermarrec 4470f32ef8 test/test_axi: change order of the tests 2018-11-12 12:59:19 +01:00
Florent Kermarrec 070cc26994 test/test_axi: use separate generator for writes cmd/data 2018-11-12 12:58:19 +01:00
Florent Kermarrec 71be616817 frontend/axi: be sure wdata is available before sending the command to the controller 2018-11-09 11:33:01 +01:00
Florent Kermarrec 9a950f051a ecc: update core/test 2018-10-12 17:13:53 +02:00
Florent Kermarrec 1bc016cf6c test: add test_examples 2018-10-01 11:29:08 +02:00
Florent Kermarrec f7f8169883 test: update downconverter/upconverter 2018-10-01 11:18:54 +02:00
Florent Kermarrec b145b0c338 frontend/axi: fix write response implementation 2018-09-18 15:24:41 +02:00
Florent Kermarrec 461b076624 frontend/ecc: add ecc adapter 2018-09-16 01:01:45 +02:00
Florent Kermarrec c84b58735a frontend: add initial ecc code (still need to be integrated) 
Works but all combinatorial, will maybe need to be pipelined
 2018-09-15 23:37:59 +02:00
Florent Kermarrec 849b1f6c35 frontend/axi: generate rlast signal 2018-09-06 11:11:17 +02:00
Florent Kermarrec 1fa73e4718 test: update 2018-09-06 11:10:45 +02:00
Florent Kermarrec f6797a16bb test/test_axi: add burst wrap test and fix code 2018-08-29 18:47:40 +02:00
Florent Kermarrec c15c47497a test/test_axi: split reads/writes generators 2018-08-28 14:09:12 +02:00
Florent Kermarrec 95cb7cdba5 test: rename read/write generators to handlers 2018-08-28 13:40:50 +02:00
Florent Kermarrec 10229d1e7d test/test_axi: improve test_axi2native 2018-08-28 13:39:11 +02:00
Florent Kermarrec 6a46ea3052 test/test_bist: add generator test, remove async test 2018-08-28 11:50:11 +02:00
Florent Kermarrec 7a5ac75e22 test/test_axi: improve test_axi2native 2018-08-27 18:39:36 +02:00
Florent Kermarrec c846b8b1c7 frontend/axi: add burst support (fixed/incr) 2018-08-27 16:21:12 +02:00
Florent Kermarrec 57157345cf frontend: add initial AXI support 2018-08-21 13:39:46 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
Florent Kermarrec c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec 697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Felix Held 72b1b109b7 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:22:08 +11:00
Florent Kermarrec 25d5674f33 test: remove test_bitslip (now in litex) 2017-04-24 18:49:20 +02:00
Florent Kermarrec 98d9f1ffc0 test/test_bitslip: simplify BitSlipModel 2017-02-10 13:18:11 +01:00
Florent Kermarrec 062177502b phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3) 2017-02-10 08:59:13 +01:00
Florent Kermarrec 99550968e7 test: move BISTDriver to common and use it in test_bist_async 2017-01-17 15:18:10 +01:00
Florent Kermarrec d213a628f8 test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator) 2017-01-17 14:35:34 +01:00
Florent Kermarrec 40168db0b4 test/test_bist: create BISTDriver to simplify test code 2017-01-17 14:31:24 +01:00
Florent Kermarrec c56f90e865 test/test_bist: simplify and test modules directly not through CSR 2017-01-17 14:14:50 +01:00
Florent Kermarrec ad304c8997 test: convert to python unittests and some cleanup 2017-01-17 13:18:11 +01:00
Tim 'mithro' Ansell c142db3966 Creating a utility module for easily scoping the LiteDRAMBISTChecker module. 2016-12-19 17:49:24 +01:00
Florent Kermarrec aac61f346e test: start fixing bist_tb 2016-12-17 19:24:12 +01:00
Tim 'mithro' Ansell e21b45b608 Merge remote-tracking branch 'upstream/master' into bist 2016-12-17 18:15:59 +01:00
Tim 'mithro' Ansell bc75d4f3d5 bist: Reworking as suggested by Florent. 2016-12-17 17:49:47 +01:00
Tim 'mithro' Ansell f1ad8991a4 bist: Working on improving the names of things. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 8ff2f8779b bist: Adding "halt on error" functionality. 
Also include ability to see address of error and expected verse actual
data values.

Extend the test bench to test this functionality.
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench. 
Move a bunch of common code into common.py
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell dc14a98bf4 bist: s/shoot/start/ 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 086b905e59 bist: Improve the basic test bench a little. 2016-12-17 14:09:50 +01:00