76caff5417
litedram_gen: add initial FIFO support
2020-01-14 18:19:32 +01:00
7d13136cdb
phy/model: small cleanup and add TODOs
2020-01-14 11:17:23 +01:00
c07f4a1f1b
gen: add l2_data_width to kwargs
2020-01-13 17:31:17 +01:00
b77af48d50
modules/H5TC4G63CFR: cleanup
2020-01-13 17:05:46 +01:00
7d8287b57a
Merge pull request #98 from Marrkson/master
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ADD: KX2 DDR3 module
2020-01-13 17:04:08 +01:00
53887fcb8e
ADD: KX2 DDR3 module
2020-01-13 14:05:38 +01:00
6f35465c0b
frotend/wishbone: avoid NextValue(count, 0) duplication
2020-01-13 13:19:25 +01:00
721c84bad0
frontend/wishbone: add efficient wishbone downconvert, improve DRAM access efficiency from CPU on boards with small native data_width.
2020-01-13 12:58:15 +01:00
34e6c24d72
frontend/wishbone: add write data buffer to avoid stalling wishbone while waiting for wdata.ready
2020-01-10 14:27:05 +01:00
1d2bc922b8
frontend/fifo: get back to original simple design and add test
2020-01-07 15:40:09 +01:00
d1b603ae6c
CONTRIBUTORS: update
2020-01-07 09:46:54 +01:00
c858890213
CONTRIBUTORS: update
2020-01-07 09:45:36 +01:00
9523386e2c
Merge pull request #97 from pdp7/master
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add 32MB SDRAM for hadbadge
2020-01-07 09:42:00 +01:00
5d8d75f6cd
add 32MB SDRAM for hadbadge
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Add AS4C32M8SA-7TCN 32MB SDRAM used on cartridge PCB
by Jacob Creedon for the Hackaday Supercon ECP5 badge.
These changes were orginally made by Michael Welling:
https://github.com/mwelling/litedram
KiCad design files for the SDRAM cartridge:
https://github.com/jcreedon/dram-cart/
The SDRAM cartridge PCB is shared at:
https://oshpark.com/shared_projects/IQSl2lid
shared DigiKey cart of the parts:
https://www.digikey.com/short/p1ct1h
More information in this blog post:
https://blog.oshpark.com/2019/12/20/
Hackaday Supercon 2019 badge PCB design:
https://github.com/Spritetm/hadbadge2019_pcb
2020-01-06 11:39:10 +01:00
a234dae338
frontend/fifo: add initial FIFO (to create large FIFOs in DRAM)
2020-01-06 10:17:46 +01:00
8dae0c0c7f
setup.py: add pyyaml to install_requires
2019-12-03 15:44:44 +01:00
eddd6e4eaf
modules/init: add DDR4 fine refresh mode support: x1, x2 and x4 (x1=previous and default behavior)
2019-12-03 12:20:32 +01:00
6c9c45f313
core/controller: cleanup ControllerSettings
2019-12-03 12:16:50 +01:00
73d614ef27
frontend/wishbone: remove LiteDRAMWishbone2AXI (can be replaced with LiteX's Wishbone2AXILite)
2019-11-30 11:06:41 +01:00
aa1ce68896
global: improve presentation/readability
2019-11-30 10:53:11 +01:00
ac4b339a6f
test/reference: update init headers
2019-11-15 19:45:39 +01:00
3fa4397224
Merge pull request #95 from gsomlo/gls-dfii-nphases
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init: improve legibility of generated/sdram_phy.h (cosmetic)
2019-11-15 19:42:27 +01:00
bdcecad76f
init: improve legibility of generated/sdram_phy.h (cosmetic)
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Use DFII_NPHASES constant (defined earlier in the file) to size the
two 'sdram_dfii_pix_[wrdata|rddata]_addr' arrays, instead of a bare
number. Additionally, ensure the first array element is indented by
a tab, same as the ones following it.
2019-11-12 14:06:47 -05:00
08325dd04e
Merge pull request #94 from mithro/lpddr-fix
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Fix broken LPDDR support.
2019-10-30 14:28:53 -07:00
746329cb43
Fix broken lpddr support.
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Fixes #93 .
2019-10-30 13:51:05 -07:00
401554f94c
Merge pull request #92 from gsomlo/gls-assert-width
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frontend/[axi,wishbone]: add data_width match assertion, add base_address to LiteDRAMWishbone2Native
2019-10-25 12:25:07 +02:00
7356d3b15d
frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native
2019-10-24 11:31:56 -04:00
24203cfc7b
frontend/axi: add assertion on matching axi, native port data_width
2019-10-23 10:01:42 -04:00
d84e1b4ac5
frontend/axi: add assert on axi.address_width and base_address
2019-10-18 18:30:39 +02:00
1d037d2a64
frontend/axi: add base_address parameter to LiteDRAMAXI2Native
2019-10-17 12:16:15 +02:00
5d1a9847aa
core: add LiteDRAMCore (ControllerInjector from LiteX)
2019-09-29 14:42:41 +02:00
d647abd026
gen: fix with_wishbone
2019-09-23 15:54:53 +02:00
db97203877
gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore
2019-09-23 12:55:14 +02:00
adf481f1d5
gen: disable peripherals that are not used when cpu_type is None
2019-09-23 10:16:47 +02:00
233191939e
gen: change CSR config names, switch to csr_expose/csr_align
2019-09-23 09:12:40 +02:00
da408a3982
gen: fix default csr_port_align value
2019-09-23 09:05:54 +02:00
bac66aa08f
gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core.
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The CSR alignment and base can be specified (which mostly affects
the generation of csr.h) andwe stop trying to copy the init code
that we haven't generated
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:58:16 +02:00
afbf709767
We had the address and data bus sizes mixed up
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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-23 08:51:04 +02:00
d93dded624
frontend/wishbone: add data_width assertions
2019-09-18 21:12:23 +02:00
f586aada1c
phys: improve presentation (add separators, better indent)
2019-09-11 09:50:46 +02:00
783258c97f
phys: use dfi instead if self.dfi internally
2019-09-11 09:00:36 +02:00
59c1289432
phy/usddrphy: move DDR4DFIMux to dfi.py
2019-09-11 08:57:58 +02:00
f861d99903
core/refresher: improve naming/parameters of refresh postponing
2019-09-11 08:38:22 +02:00
dc1bb53a88
phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common
2019-09-11 08:00:54 +02:00
509f60652a
README: add periodic refresh/ZQ short calibration.
2019-09-09 18:05:17 +02:00
40b4c62889
test/test_init: fix
2019-09-09 15:17:43 +02:00
5b48eb278a
test/test_init: delete generated file
2019-09-09 15:08:01 +02:00
188b6a8feb
add ZQ periodic short calibration support (default to 1s)
2019-09-09 15:07:38 +02:00
6e176d40ac
init: split by memtype
2019-09-09 12:10:48 +02:00
0b24b817e3
test: add test_init with sdr/ddr3/ddr4 references
2019-09-09 11:45:10 +02:00
Florent Kermarrec
Mark
Drew Fustini
Gabriel Somlo
Tim Ansell
Benjamin Herrenschmidt