b8cd26fa52
test/refefence: Update.
2021-05-18 11:26:40 +02:00
0877a81b4b
test/test_init: Add simple way to update references.
2021-05-18 11:26:19 +02:00
63358ee666
test/reference: Update.
2021-04-28 18:21:27 +02:00
886f60d32c
test/reference: Update.
2021-04-23 11:26:30 +02:00
7028944acd
lpddr4: add missing copyright comments
2021-04-01 10:07:02 +02:00
e860d86f3f
lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default)
2021-03-25 15:31:58 +01:00
0ecb1340f5
lpddr4/test: fixes: use 2tCK write preamble, update read latency
2021-03-25 15:31:05 +01:00
5c6796b92a
lpddr4: change MRW command encoding to avoid changing BIOS code
2021-03-25 15:30:48 +01:00
eb1d900c24
lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE
2021-03-25 15:29:17 +01:00
4415a3eaf5
lpddr4: improve simulation and Verilator tests runner
2021-03-25 15:19:16 +01:00
2ab763ac5e
lpddr4: add double-rate PHY, clean up and improve PHY implementation
2021-03-25 15:19:16 +01:00
183f1643aa
lpddr4: add support for MASKED-WRITE
2021-03-25 15:19:16 +01:00
05ed238829
lpddr4: split implementation into multiple files in separate directory
2021-03-25 15:19:16 +01:00
ee9c2b4cf7
lpddr4: implement ZQC through MPC and include it in init sequence
...
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
2021-03-25 15:19:16 +01:00
6943a1a4a5
lpddr4: initial PHY logic and simulation tests
2021-03-25 15:19:08 +01:00
2d021c842e
test/reference: update.
2021-02-16 18:35:53 +01:00
2c60861929
Merge pull request #232 from antmicro/jboc/init-mr
...
init: make the write leveling MR bit configurable
2021-02-02 09:36:46 +01:00
b3ce582891
test: update ddr3 and ddr4 reference headers to new MR_WLVL defines
2021-01-29 12:49:19 +01:00
a1e7d805ec
test: improve error messages when comparing files in test_init.py
2021-01-28 17:44:13 +01:00
c29c898af4
platforms/targets: switch to LiteX-Boards.
2021-01-04 14:11:32 +01:00
103072c68a
test/reference: update.
2020-12-17 18:21:53 +01:00
b6252345af
test/reference: update ddr4.
2020-11-17 17:12:02 +01:00
df73b982ee
test/reference: update
2020-10-12 18:50:31 +02:00
39178ce460
test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
2020-10-02 12:30:19 +02:00
f8ee596464
test/reference: update.
2020-09-30 19:49:38 +02:00
6d063b196c
test/reference: update.
2020-09-30 18:06:48 +02:00
c4d7083677
test/reference: update.
2020-09-30 13:29:39 +02:00
7ccb7d8f16
test/reference: update.
2020-09-24 15:03:35 +02:00
8525a27762
test/reference: update.
2020-09-15 20:00:55 +02:00
e56f74e08b
test/reference: update.
2020-09-07 19:37:03 +02:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
198bcbab67
test/reference: update.
2020-08-07 23:14:09 +02:00
16fd46bf35
frontend: rename adaptation to adapter.
2020-08-05 11:10:42 +02:00
02e67ec7c5
Merge pull request #192 from antmicro/jboc/port-adaptation
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Implement LiteDRAMNativePortUpConverter with mode="both"
2020-07-28 19:02:33 +02:00
c4c8803f4f
Merge pull request #204 from antmicro/jboc/spd-read
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Add DDR4 SPD EEPROM data parser
2020-06-04 08:54:59 +02:00
8fedc3fcd2
frontend/fifo: increase FIFO level after data has actually been written
2020-06-03 16:13:28 +02:00
863c45a114
test/spd_data: add missing files to tracking
2020-06-02 15:19:53 +02:00
a8f2c044c9
modules: add DDR4SPDData parser
2020-06-02 12:16:41 +02:00
d62fd24c81
Merge pull request #201 from antmicro/jboc/spd-read
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modules/spd: save SPD data in SDRAMModule
2020-06-01 21:16:58 +02:00
4233f86112
modules/spd: save SPD data in SDRAMModule to allow for runtime verification
2020-06-01 16:56:41 +02:00
639a31fdd2
test/test_timing: update test_txxd_controller.
2020-05-20 23:40:01 +02:00
fe48a9290c
test/reference: update.
2020-05-19 08:16:11 +02:00
22bd01c014
frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
2020-05-13 17:14:42 +02:00
efe9a44c93
frontend/adaptation: clean up LiteDRAMNativePortUpConverter code
2020-05-11 16:47:43 +02:00
2f35e9714d
frontend/adaptation: fix error when read follows write to the same address
2020-05-11 16:11:40 +02:00
1587ee3611
frontend/adaptation: use port.cmd.last instead of port.flush in up-converter
2020-05-11 15:28:32 +02:00
35fa91c055
test/crossbar: up-conversion with mode="both" should be working now
2020-05-11 14:56:39 +02:00
9b90a56e07
frontend/adaptation: combine read/write port up-converters and extend tests
2020-05-11 14:56:39 +02:00
762cd6d0f1
test/adaptation: add port converter tests with mode="both"
2020-05-11 14:56:39 +02:00
7a0f7a7ead
test/common: fix error in test data
2020-05-11 14:56:39 +02:00
Florent Kermarrec
Jędrzej Boczar