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1059 Commits

Author SHA1 Message Date
enjoy-digital eacfbd8055
Merge pull request #122 from antmicro/jboc/benchmark 
Load benchmark configuration from YAML
 2020-01-30 16:08:30 +01:00
Jędrzej Boczar f6973aa9d7 test: load benchmark configurations from YAML file 2020-01-30 15:39:29 +01:00
Florent Kermarrec 090620c9d6 frontend/dma: add optional CSR control 2020-01-30 15:21:37 +01:00
Jędrzej Boczar 096de78c63 test: fix `setup.py test` failing due to import error 
because of relative import the script has to be run as:
    python -m test.run_benchmarks
 2020-01-30 14:11:52 +01:00
enjoy-digital e17e6e34d8
Merge pull request #118 from antmicro/jboc/benchmark 
Add a script for running LiteDRAM benchmarks
 2020-01-30 13:31:11 +01:00
Jędrzej Boczar bb4f6106ee test: print benchmarks summary 2020-01-30 10:50:08 +01:00
Jędrzej Boczar e822e6be9f test: calculate benchmark bandwidth and efficiency 2020-01-30 10:19:17 +01:00
Jędrzej Boczar 804a9b3727 test: add script for running multiple benchmarks and parsing results 2020-01-29 17:03:20 +01:00
enjoy-digital a35a1f7790
Merge pull request #116 from antmicro/jboc/benchmark 
test: add command line arguments for BIST base/length/random
 2020-01-28 15:42:27 +01:00
Jędrzej Boczar 502e6c663c test: add command line arguments for BIST base/length/random 2020-01-28 15:03:36 +01:00
enjoy-digital 72e65e697f
Merge pull request #115 from antmicro/ddr4-model 
phy/model: add burst_length value for ddr4 memories
 2020-01-28 14:48:00 +01:00
Piotr Binkowski cd25106fc1 phy/model: add burst_length value for ddr4 memories 2020-01-28 14:23:35 +01:00
enjoy-digital 6b91c1fa86
Merge pull request #111 from antmicro/write-latency 
phy/model: simulate write latency
 2020-01-28 14:05:16 +01:00
Piotr Binkowski f9d00f137b phy/model: simulate write latency 2020-01-28 12:38:17 +01:00
Florent Kermarrec 586eb39b1d test: add initial benchmark test 2020-01-28 12:07:22 +01:00
Florent Kermarrec e4f901f070 phy/model: review/simplify initialization 2020-01-27 21:29:08 +01:00
enjoy-digital 9c00255483
Merge pull request #104 from antmicro/phy-model-init 
phy/model: add support for initializing memory from file
 2020-01-27 20:54:51 +01:00
Florent Kermarrec e5e4f528d4 examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright 2020-01-27 18:30:24 +01:00
Florent Kermarrec bb683a69ea litedram_gen: cleanup/rename CRGs, update copyrights 2020-01-27 18:29:52 +01:00
Florent Kermarrec 4d19620a37 litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY) 2020-01-27 18:20:16 +01:00
enjoy-digital b1f087959b
Merge pull request #105 from ximinity/gen_ecp5 
WIP: litedram_gen: add ecp5 support
 2020-01-27 17:50:47 +01:00
Piotr Binkowski a3fc1b9219 phy/model: add support for initializing memory from file 2020-01-27 15:41:08 +01:00
Florent Kermarrec 74f72f91a0 phy/usddrphy: reorder primitives parameters/signals 2020-01-26 21:14:20 +01:00
Florent Kermarrec 11293dcccc phy/s7ddrphy: reorder primitives parameters/signals 2020-01-26 21:00:57 +01:00
Florent Kermarrec f252e8b27f phy/usddrphy: simplify dqs_serdes_pattern 2020-01-26 12:55:14 +01:00
Florent Kermarrec 72da321fa4 phy/usddrphy: cleanup primitives instances 2020-01-26 12:44:48 +01:00
Florent Kermarrec 33c5d7b87e phy/s7ddrphy: simplify dqs_serdes_pattern 2020-01-26 12:04:55 +01:00
Florent Kermarrec 2072ce77b0 phy/s7ddrphy: cleanup primitives instances 2020-01-26 12:00:14 +01:00
Stefan Schrijvers 340a796129
litedram_gen: add ecp5 support 2020-01-25 18:59:26 +01:00
Florent Kermarrec f4de17b8e6 phy/ecp5ddrphy: reorder signals/parameters on primitives 2020-01-25 17:00:18 +01:00
Florent Kermarrec e0966e2ed3 phy/ecp5ddrphy: improve presentation/readability 2020-01-25 15:30:00 +01:00
Florent Kermarrec bb1b431184 test/test_init: use max_sdram_size of 1GB 2020-01-24 10:46:29 +01:00
Florent Kermarrec dc16d971ad modules: add M12L16161A 2020-01-22 16:31:13 +01:00
Florent Kermarrec ba9134a9a8 litedram_gen: set min_l2_data_width to 0 (l2_data_width will use controller's data_width) 2020-01-20 19:16:00 +01:00
Florent Kermarrec cee3a43685 modules: add M12L64322A 2020-01-18 21:16:19 +01:00
Florent Kermarrec 6105ae371e modules: be sure tRFC use tuple on all modules 2020-01-16 10:48:51 +01:00
Florent Kermarrec 2d40126e59 litedram_gen: improve indent 2020-01-16 10:47:15 +01:00
Florent Kermarrec 36e8ae9df1 litedram_gen: remove underscore in AXI names to ease packaging 2020-01-15 13:01:04 +01:00
Florent Kermarrec 61b19e2aaf litedram_gen: improve flexibility to define user ports 2020-01-15 12:57:33 +01:00
Florent Kermarrec 76caff5417 litedram_gen: add initial FIFO support 2020-01-14 18:19:32 +01:00
Florent Kermarrec 7d13136cdb phy/model: small cleanup and add TODOs 2020-01-14 11:17:23 +01:00
Florent Kermarrec c07f4a1f1b gen: add l2_data_width to kwargs 2020-01-13 17:31:17 +01:00
Florent Kermarrec b77af48d50 modules/H5TC4G63CFR: cleanup 2020-01-13 17:05:46 +01:00
enjoy-digital 7d8287b57a
Merge pull request #98 from Marrkson/master 
ADD: KX2 DDR3 module
 2020-01-13 17:04:08 +01:00
Mark 53887fcb8e ADD: KX2 DDR3 module 2020-01-13 14:05:38 +01:00
Florent Kermarrec 6f35465c0b frotend/wishbone: avoid NextValue(count, 0) duplication 2020-01-13 13:19:25 +01:00
Florent Kermarrec 721c84bad0 frontend/wishbone: add efficient wishbone downconvert, improve DRAM access efficiency from CPU on boards with small native data_width. 2020-01-13 12:58:15 +01:00
Florent Kermarrec 34e6c24d72 frontend/wishbone: add write data buffer to avoid stalling wishbone while waiting for wdata.ready 2020-01-10 14:27:05 +01:00
Florent Kermarrec 1d2bc922b8 frontend/fifo: get back to original simple design and add test 2020-01-07 15:40:09 +01:00
Florent Kermarrec d1b603ae6c CONTRIBUTORS: update 2020-01-07 09:46:54 +01:00