12ddc135be
litedram/gen: add description and switch to argparse
2019-08-28 08:07:20 +02:00
2bdeda021b
move standalone core generation to litedram package and make it usable externally
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When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"
2019-08-28 07:19:30 +02:00
0dde125740
examples/litedram_gen: fix #!/usr/bin/env python3 location
2019-08-28 07:09:58 +02:00
602ff8be81
examples: switch to YAML config files
2019-08-28 07:08:10 +02:00
fb28f791c8
core/refresher: remove load/load_count on RefreshTimer (not used)
2019-08-16 08:52:36 +02:00
1c69f49760
core/controller: allow user provided Refresher
2019-08-16 08:39:08 +02:00
b64daba711
core/controller: add separators, ease readibility
2019-08-16 08:37:08 +02:00
338d18dba0
core/refresher: add capability to accumulate N refreshs and execute the N refreshs together
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Being able to accumulate refreshs allow reducing the number of interruptions to the Controller from 1 every tREFI cycles to 1 every N*tREFI cycles.
2019-08-14 09:57:24 +02:00
818c4ca9db
core/refresher: another cleanup pass
2019-08-14 09:07:49 +02:00
80c8ecf477
core/multiplexer: rewrite arbiter comment
2019-08-14 08:59:49 +02:00
37db41648e
core/refresher: another cleanup pass
2019-08-14 08:50:34 +02:00
f0592ff89f
core/refresher: add comments
2019-08-14 08:30:25 +02:00
de38b52eb6
core/refresher: rename RefreshGenerator to RefreshSequencer and simplify
2019-08-14 08:08:30 +02:00
8573c22cc1
phy/gensdrphy: add assertions on length of pads.dq/pads.dq
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Allow detecting platform file issues similar to #88 , #89 earlier.
2019-08-04 15:06:34 +02:00
6c53996a70
core/refresher: reduce refresh period by one cycle
2019-07-24 08:18:04 +02:00
afb6d0a15e
core/refresher: reduce RefreshGenerator start delay by 1 cycle
2019-07-24 08:01:54 +02:00
b543286d06
test/test_refresh: add Refresher test
2019-07-23 22:31:27 +02:00
7daf3551f6
test/test_bist: remove vcd generation (only useful for debug)
2019-07-23 21:46:03 +02:00
b4125fa50f
test/test_refresh: add RefreshTimer test
2019-07-23 21:44:09 +02:00
9584c2fe88
test: remove use of rand_wait, rename rand_level to random
2019-07-23 21:14:17 +02:00
0eef5d4d55
test: add test_refresh with simple RefreshGenerator test
2019-07-23 16:36:21 +02:00
93488009c9
test: rename test_timing_controllers to test_timing
2019-07-23 16:05:31 +02:00
8cf561d620
test/test_timing_controllers: add simple tFAWController tests
2019-07-23 15:58:26 +02:00
3ae666d015
test/test_timing_controllers: add simple tXXDController tests
2019-07-23 15:48:32 +02:00
394a49a759
test: add test_timing_controllers with tXXDController test
2019-07-23 12:40:40 +02:00
6e3f7691c5
core: move timing controllers to common
2019-07-23 12:39:14 +02:00
54cdc7f4cb
test: -x on tests
2019-07-23 12:16:44 +02:00
2ecb0534ec
frontend/ecc: move generic part of ECC to LiteX
2019-07-13 11:47:13 +02:00
8646b2e2c4
test/test_adaption: use same DUT for up/down converter tests
2019-07-13 10:52:41 +02:00
9f9fed02f6
test: merge test_downconverter/test_upconverter in a single test_adaptation file
2019-07-13 10:31:30 +02:00
fc41751080
frontend/dma: simplify rsv_level expose
2019-07-05 11:30:57 +02:00
88835de734
Merge pull request #86 from sergachev/master
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dma: expose reservation level in the reader
2019-07-05 11:29:26 +02:00
f145287fdc
dma: expose reservation level in the reader
2019-07-05 09:57:13 +02:00
f018c9e268
add CONTRIBUTORS file and add copyright header to all files.
2019-06-23 23:59:10 +02:00
18dda2db54
phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits
2019-06-22 10:46:02 +02:00
690e4f848f
README: fix ECP5 frequency ratio
2019-06-16 21:35:46 +02:00
67de3cee14
Merge pull request #85 from antmicro/fix_databits
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PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
2019-06-13 16:55:11 +02:00
24851c9a3b
PhySettings: set missing databits parameter for S6QuarterRateDDRPHY
2019-06-13 15:41:47 +02:00
fef530366a
test: clean test_downconverter/test_upconverter (thanks sb0)
2019-06-13 09:15:09 +02:00
7fbe0b712c
Merge pull request #84 from open-design/is42s16320
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modules: SDRAM: add IS42S16320 support
2019-06-02 18:38:12 +02:00
5c66547334
modules: SDRAM: add IS42S16320 support
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The IS42S16320D-7TL 32Mx16 512Mb SDRAM chips
are used in Terasic DE1-SoC and Terasic DE2-115
FPGA development boards.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-01 15:05:58 +03:00
8e2df17747
modules: fix tRFC change on MT16KTF1G64HZ
2019-05-28 22:42:45 +02:00
bc88cfa6f7
modules: allow tRFC to be defined in ck or ns, fix some DDR3/DDR4 definitions (thanks @ambrop72 for the review)
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In some DDR3/DDR4 datasheet, tRFC is defined in ck or in ns. Allow definition in ck or ns
and review all the modules.
2019-05-28 10:17:39 +02:00
fbd7ae3e62
modules: make IS43TR16128B consistent with others SDRAMModules
2019-05-28 10:02:02 +02:00
02448a3670
Merge pull request #83 from ambrop72/IS43TR16128B_125K
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modules/ddr3: add IS43TR16128B_125K
2019-05-28 09:59:57 +02:00
d1089701d4
modules/ddr3: add IS43TR16128B_125K
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This is the chip that is actually on my Arty A7 100T (there is no mention of this chip in the Arty reference, which claims it is MT41K128M16JT-125).
2019-05-27 19:36:38 +02:00
da68e21bad
Merge pull request #82 from gsomlo/gls-expose-csr
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examples/litedram_gen: allow direct access to CSR (I/O) registers
2019-05-17 21:27:45 +02:00
65451f426a
examples/litedram_gen: allow direct access to CSR (I/O) registers
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
[florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]
2019-05-16 15:05:30 -04:00
50e1d478db
PhySettings: add databits to allow SoC to compute memory size more easily
2019-05-10 15:44:44 +02:00
b93412bbdc
examples: remove verilog simulation
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Simulation was here just to show how to do system level simulation adn required
external component to work (stadalone init).
2019-05-10 13:05:48 +02:00
Florent Kermarrec
Ilia Sergachev
Mateusz Holenko
Antony Pavlov
Ambroz Bizjak
Gabriel L. Somlo