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1223 Commits

Author SHA1 Message Date
Owen Kirby 805a37447c Add support for TDQS mode. 
This adds an optional argument to add_electrical_settings() that can
enable the TDQS mode for x8 DDR3 modules. Normally this would be used
when mixing x4 and x8 modules (eg: heterogenous DIMMS), but it can
also workaround boards with missing or broken DM signals.
 2020-07-26 15:51:07 -07:00
Florent Kermarrec c01e86865f phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. 2020-07-24 11:07:15 +02:00
Florent Kermarrec f51052f8b7 core/controller: fix burst_length regression introduced by #206. 2020-07-18 23:06:11 +02:00
enjoy-digital c4ac887ec2
Merge pull request #206 from antmicro/jboc/gensdrphy 
Add HalfRate GENSDRPHY
 2020-07-15 08:19:37 +02:00
Jędrzej Boczar 2c5fc6621a phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6 2020-07-14 10:58:58 +02:00
Jędrzej Boczar 7f55e2e2c5 phy/gensdrphy: add half-rate PHY 2020-07-13 17:03:01 +02:00
Florent Kermarrec edd5e0ec78 phy/gensdrphy: padd clk to SDROutput/SDRInput/SDRTristate. 2020-07-08 07:00:11 +02:00
Florent Kermarrec a8fa38e286 phy/ecp5ddrphy: cosmetic cleanups. 2020-06-30 09:25:44 +02:00
Florent Kermarrec 8c339b9945 litedram_gen: update ECP5 clocking. 2020-06-29 19:30:13 +02:00
Florent Kermarrec f6cc1cdb08 litedram_gen: increase integrated_rom_size to 0x8000. 2020-06-29 19:28:11 +02:00
Florent Kermarrec 9044c10408 phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally. 2020-06-29 16:09:14 +02:00
Florent Kermarrec fa7d91a053 phy/ecp5: simplify/fix dqs_oe/dq_oe and revert BitSlip on dq_i_data. 
dq/dqs_oe was one cycle of and BitSlip on dq_i_data is required for correct initialization.
 2020-06-29 16:06:56 +02:00
enjoy-digital 8c112c709c
Merge pull request #207 from ozbenh/sim-autoinit 
dfii: Really default to HW control
 2020-06-10 10:36:05 +02:00
Benjamin Herrenschmidt 4580882c69 dfii: Really default to HW control 
Looks like there was a typo in commit
a595fe07f2
"dfii: simplify control using CSRFields"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-06-10 16:06:46 +10:00
Florent Kermarrec 52d7dbe3a6 frontend/fifo: make sure FIFO is only used on LiteDRAMNativePort, expose writer/reader fifo depth, add separators and update copyrights. 2020-06-04 09:26:13 +02:00
enjoy-digital c4c8803f4f
Merge pull request #204 from antmicro/jboc/spd-read 
Add DDR4 SPD EEPROM data parser
 2020-06-04 08:54:59 +02:00
enjoy-digital 067e8a5eb3
Merge pull request #205 from antmicro/jboc/fifo 
frontend/fifo: increase FIFO level only after data has actually been written
 2020-06-04 08:41:04 +02:00
Jędrzej Boczar e5179eb9ab gen: fix LiteDRAMFIFO parameters 2020-06-03 17:39:45 +02:00
Jędrzej Boczar 8fedc3fcd2 frontend/fifo: increase FIFO level after data has actually been written 2020-06-03 16:13:28 +02:00
Florent Kermarrec 992f80c68b litedram_gen: add Ultrascale(+) support and KCU105 config file, remove cmd_delay on 7-series (not automatically calibrated). 2020-06-03 09:35:40 +02:00
Florent Kermarrec 361d250677 litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide). 2020-06-03 09:04:00 +02:00
Florent Kermarrec 1b56dcf364 litedram_gen: add more memtype asserts, remove csr_alignment (now fixed to 32-bit). 2020-06-03 08:57:31 +02:00
Florent Kermarrec a595fe07f2 dfii: simplify control using CSRFields. 2020-06-02 16:31:33 +02:00
enjoy-digital 899462c864
Merge pull request #202 from ozbenh/sim-autoinit 
Default to HW control for sim
 2020-06-02 15:48:41 +02:00
Jędrzej Boczar 863c45a114 test/spd_data: add missing files to tracking 2020-06-02 15:19:53 +02:00
Jędrzej Boczar cbd90877b0 modules/spd: select tFAW_min_ck depending on page size 2020-06-02 12:19:38 +02:00
Jędrzej Boczar a8f2c044c9 modules: add DDR4SPDData parser 2020-06-02 12:16:41 +02:00
enjoy-digital d62fd24c81
Merge pull request #201 from antmicro/jboc/spd-read 
modules/spd: save SPD data in SDRAMModule
 2020-06-01 21:16:58 +02:00
Jędrzej Boczar 4233f86112 modules/spd: save SPD data in SDRAMModule to allow for runtime verification 2020-06-01 16:56:41 +02:00
Benjamin Herrenschmidt f3f89ed8d1 Default to HW control for sim 
(needs corresponding sdram.c fix in litex)

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-06-01 23:44:59 +10:00
Florent Kermarrec f23cb8056d litedram_gen: revert builder.build(..., regular_comb=False). 2020-05-27 19:56:00 +02:00
Florent Kermarrec d1db115d6c litedram_gen: review/simplify #197. 2020-05-27 19:42:40 +02:00
enjoy-digital a8e281f7c5
Merge pull request #197 from ozbenh/standalone-sim 
Allow generation of a standalone sim model
 2020-05-27 19:16:00 +02:00
enjoy-digital 83b9a1d798
Merge pull request #199 from antmicro/jboc/spd-read 
modules: add function for parsing SPD EEPROM dumps from BIOS firmware
 2020-05-27 14:57:16 +02:00
Benjamin Herrenschmidt d0f0c94652 phy/model: Don't generate empty mem_*.init files 
When using the SDRAM PHY model without specified init data, the
generator still generates a bunch of $readmemh for each bank
reading mem.init, mem_1.init etc... all of which are 0-sized files.

This is cumbersome especially when using a standalone model in
an external project.

This is fixed by having the default bank_init be set to a list
of "None" rather than a list of empty lists.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-22 18:09:11 +10:00
Benjamin Herrenschmidt b8d6da534f gen: Allow generation of a standalone sim model 
If the --sim argument is passed, this generates a model using
the simulation platform and simulated PHY.

Note: The data_width is set to 16 for now, which matches the
Arty. I haven't yet figured out how to extract that info from
the data we have in the .yml

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-05-22 18:09:06 +10:00
Jędrzej Boczar cbe91bcd41 modules: add function for parsing SPD EEPROM dumps from BIOS firmware 2020-05-21 16:18:34 +02:00
Florent Kermarrec 639a31fdd2 test/test_timing: update test_txxd_controller. 2020-05-20 23:40:01 +02:00
Florent Kermarrec 3c1ab76bbc litedram/common/tXXDController: only set reset to 1 when txxd is None. 
This avoids triggering a warning/error with Yosys.
 2020-05-19 13:10:32 +02:00
enjoy-digital e95af3f15b
Merge pull request #195 from enjoy-digital/bios-libs 
Init: Generate DFII defines in sdram_phy.h
 2020-05-19 08:18:38 +02:00
Florent Kermarrec fe48a9290c test/reference: update. 2020-05-19 08:16:11 +02:00
Florent Kermarrec c30910a9d2 init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. 2020-05-18 23:06:33 +02:00
Florent Kermarrec 5078b19bff core/crossbar: remove retro-compat > 6 months old. 2020-05-18 18:51:56 +02:00
Florent Kermarrec 3b105d512b modules: fix SDRAMRegisteredModule. 2020-05-15 21:39:00 +02:00
enjoy-digital b2a5685396
Merge pull request #189 from daveshah1/ddr4_rdimm_init 
Add support for DDR4 RDIMMs
 2020-05-15 21:34:43 +02:00
Florent Kermarrec 7ae4ad5b7d modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions). 2020-05-15 21:27:43 +02:00
Florent Kermarrec 1f7d9eb0b9 litedram_gen: pass FPGA speedgrade to iodelay_pll. 2020-05-14 11:44:32 +02:00
Jędrzej Boczar 22bd01c014 frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter 2020-05-13 17:14:42 +02:00
Florent Kermarrec f4871b9f13 litedram_gen: use default settings on wb_bus. 2020-05-13 14:50:06 +02:00
Jędrzej Boczar b0bde294c0 frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ 2020-05-13 10:14:00 +02:00