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1223 Commits

Author SHA1 Message Date
Gabriel Somlo e2b5602acf fix gcc warning: function used but not defined 
The 'cdelay()' function is defined in LiteX 'liblitedram', so we
should not be using 'static' to declare it before calling it from
other C source files.
 2021-05-26 10:35:28 -04:00
Florent Kermarrec b0bbe8aa75 frontend/dma/LiteDRAMDMAWriter: Fix refactoring fsm state typo. 2021-05-26 15:18:04 +02:00
Florent Kermarrec b8cd26fa52 test/refefence: Update. 2021-05-18 11:26:40 +02:00
Florent Kermarrec 0877a81b4b test/test_init: Add simple way to update references. 2021-05-18 11:26:19 +02:00
enjoy-digital afbb229308
Merge pull request #252 from antmicro/jboc/lpddr4-inc-freq 
init: generate sdram_phy.h in a way that allows to include it in multiple units
 2021-05-18 10:27:39 +02:00
Jędrzej Boczar 282c208b63 init: generate sdram_phy.h in a way that allows to include it in multiple units 2021-05-13 18:54:01 +02:00
enjoy-digital 762da8034d
Merge pull request #250 from andrewb1999/adapter-fix 
Only update UpConverter sel when input valid
 2021-05-03 16:59:55 +02:00
enjoy-digital feba854c0b
Merge pull request #249 from andrewb1999/master 
Fix adapter reverse typo
 2021-05-03 16:49:59 +02:00
Andrew Butt e97ff4aaa0 Fix adapter sel 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-05-01 17:42:07 -04:00
Andrew Butt 99990b9eae Fix adapter reverse typo 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-04-30 11:49:20 -04:00
Florent Kermarrec 63358ee666 test/reference: Update. 2021-04-28 18:21:27 +02:00
enjoy-digital 8a4311ba40
Merge pull request #248 from antmicro/jboc/lpddr4-init 
init/lpddr4: make some settings configurable via phy_settings
 2021-04-28 17:58:49 +02:00
Florent Kermarrec 6755c8438f frontend/wishbone: Fix refactoring typos (thanks jfng). 2021-04-28 17:55:18 +02:00
Florent Kermarrec 981d5a077b init: Disable DQ-DQS training on Ultrascale(+) for now (requires more testing). 2021-04-28 17:54:25 +02:00
Jędrzej Boczar 3cdce6ca53 init/lpddr4: make some settings configurable via phy_settings 2021-04-28 15:05:33 +02:00
enjoy-digital c139f9d3d4
Merge pull request #247 from andrewb1999/master 
Fix UpConverter reversed write mask
 2021-04-27 18:19:32 +02:00
Florent Kermarrec bd80053ebf frontend/wishbone: Rewrite/Simplify using an FSM (as it was originally) and also add Abort support. 2021-04-27 16:08:15 +02:00
Andrew Butt b4a2b7f9b0 Fix UpConverter reversed write mask 
Signed-off-by: Andrew Butt <andrewb1999@gmail.com>
 2021-04-27 02:08:31 -04:00
Florent Kermarrec 886f60d32c test/reference: Update. 2021-04-23 11:26:30 +02:00
Florent Kermarrec 6a80773bc8 init: Simplify SDRAM_PHY_MODULES define: this is just SDRAM_PHY_DATABITS/8. 2021-04-23 09:05:32 +02:00
Florent Kermarrec 103534d0e8 init: Enable DQ-DQS training on 7-Series (except Artix7) and Ultrascale. 2021-04-22 18:34:18 +02:00
Florent Kermarrec 3f4b6f661c init: Cleanup PHY lists in capabilities. 2021-04-22 17:38:14 +02:00
enjoy-digital fda8689142
Merge pull request #244 from antmicro/jboc/dq-dqs-training 
Add DQ-DQS training for LPDDR4 PHY
 2021-04-22 17:28:10 +02:00
Florent Kermarrec 6256031d51 bench: Update build directories and add rst in CRG (triggered on CPU reboot). 2021-04-22 14:57:13 +02:00
Florent Kermarrec c2a779df46 bench: Update test targets (add_csr no longer required). 2021-04-19 13:40:17 +02:00
Jędrzej Boczar ebaf63479d init/lpddr4: modify pull-down drive strength to improve signal quality 2021-04-16 15:35:35 +02:00
Jędrzej Boczar 98f2f24e20 init: enable DQ-DQS training for LPDDR4 PHYs with output delays 2021-04-16 15:12:44 +02:00
enjoy-digital 26c9f82c1b
Merge pull request #236 from jersey99/master 
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vex…
 2021-04-01 19:00:51 +02:00
enjoy-digital e898507409
Merge pull request #242 from antmicro/jboc/lpddr4-copyrights 
lpddr4: add missing copyright comments
 2021-04-01 19:00:15 +02:00
enjoy-digital 172add8dfc
Merge pull request #240 from antmicro/jboc/lpddr4 
lpddr4: add a local README with a summary of the code
 2021-04-01 18:54:42 +02:00
enjoy-digital 478157560f
Merge pull request #241 from antmicro/jboc/lpddr4-init-fix 
Fix Python header generation for LPDDR4
 2021-04-01 18:53:38 +02:00
Jędrzej Boczar 7028944acd lpddr4: add missing copyright comments 2021-04-01 10:07:02 +02:00
Jędrzej Boczar c12e832bcb init: fix python header generation 
With the previous code lines included python variable names instead of integers, e.g.
("ZQ Calibration start", MPC.ZQC_START, SpecialCmd.MPC, dfii_command_we|dfii_command_cs, 200)
which failed as these names were not being imported.
 2021-03-31 15:58:43 +02:00
Jędrzej Boczar 13db84ceb5 lpddr4: add a local README with a summary of the code 2021-03-31 12:51:34 +02:00
enjoy-digital 996d0add26
Merge pull request #224 from antmicro/jboc/lpddr4 
Add LPDDR4 PHY
 2021-03-31 09:35:06 +02:00
enjoy-digital f5e7c39776
Merge pull request #238 from antmicro/jboc/refresh-all-banks 
core/refresher: use A10=1 for an all-banks REF
 2021-03-31 08:50:25 +02:00
enjoy-digital df2a06584b
Merge pull request #237 from antmicro/jboc/dfii-bankbits 
core: use wider DFI address/bank if PHY requires it
 2021-03-31 08:48:32 +02:00
Florent Kermarrec 04334ae141 phy/s7ddrphy/usddrphy: Use explicit sys clock domain on ClockSignal/ResetSignal. 
Improve readability.
 2021-03-30 08:51:44 +02:00
Florent Kermarrec 5cd192a708 bench: Remove soc_sdram import (No longer useful and deprecated). 2021-03-30 08:49:54 +02:00
Jędrzej Boczar 06b30979dd lpddr4/s7phy: add with_odelay parameter and Artix/Kintex/Virtex variants 2021-03-25 15:31:58 +01:00
Jędrzej Boczar e07198ac57 lpddr4/utils: simplify ConstBitSlip 2021-03-25 15:31:58 +01:00
Jędrzej Boczar e860d86f3f lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar f282d809d1 lpddr4: remove old fixme comments 2021-03-25 15:31:58 +01:00
Jędrzej Boczar a64cb58753 core/refresher: use A10=1 for all banks REF 
This is needed because newer DRAMs like LPDDR4 or DDR5 have
separate commands for per-bank refresh and all banks refresh.
Other DRAM types ignore address for REF commands.
 2021-03-25 15:31:58 +01:00
Jędrzej Boczar a21b70e061 init: revert bitslips changed to 16 for phys other than S7LPDDR4PHY 2021-03-25 15:31:58 +01:00
Jędrzej Boczar f3a0a7d038 lpddr4/s7phy: remove OE delay CSRs, use fixed, tested values 2021-03-25 15:31:58 +01:00
Jędrzej Boczar ba57791c1d lpddr4/s7phy: extend time of holding output enable on tristate lines 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 58235f478e lpddr4/init: increase CA/DQ Vref to 30.4% (yields better results) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 693695f067 lpddr4/init: initialize all More Registers (even if setting defaults) 2021-03-25 15:31:58 +01:00
Jędrzej Boczar 0ecb1340f5 lpddr4/test: fixes: use 2tCK write preamble, update read latency 2021-03-25 15:31:05 +01:00