431e563a39
common: move cmd/wdata/rdata descriptions and add minimal description of signals.
2020-11-09 12:06:02 +01:00
1d450bac57
common/BitSlip: reset value to value.reset.
2020-10-08 19:40:40 +02:00
3fddff3a11
common/BitSlip: shift output by one bit (allow 1 cycle latency on writes), set reset value to cycles*dw-1.
2020-10-08 17:37:24 +02:00
732df04413
common/Bitslip: add assert on cycles.
2020-10-08 17:16:21 +02:00
c16628531a
common/BitSlip: allow passing i/o signals as parameters.
2020-10-08 16:56:22 +02:00
329c9904f7
common/DQSPattern: add transmission order, minor simplification on USDDRPHY.
2020-10-02 12:26:57 +02:00
6a23bd623b
phy/ecp5/s7/usddrphy: simplify dq/dqs tristate using TappedDelayLine.
2020-10-02 09:37:32 +02:00
d12caf1e0c
common: add TappedDelayLine to simplify delays on control signals.
2020-10-01 18:29:35 +02:00
a5a4a422dd
phy/core: move rd/wrcmdphase and computation to Multiplexer.
...
rd/wrcmdphases are always computated as (rd/wrphase-1)%nphases so it's not useful
to expose them as PhySettings. rd/wrcmdphases are now directly computated in
Multiplexer and static/dynamic rd/wrphases are supported.
2020-10-01 11:26:04 +02:00
207b8f48bb
common: simplify/rename get_sys_phase (cmd_phase is always -1 can be calculated on phys).
2020-09-30 19:38:43 +02:00
68e9a02a55
litedram/common: add cl/cwl values for DDR4 data rates from 1333MT/s to 2666MT/s.
2020-09-29 19:46:39 +02:00
cf45ca48bc
s7ddrphy/usddrphy: add cmd_delay parameter and pass cmd_latency/cmd_delay to PhySettings/Software.
2020-09-07 18:50:01 +02:00
3bab6f2024
common/PHYPadsReducer: make Cat optional (disabled by default).
2020-09-04 11:10:48 +02:00
41c8ac637d
common/PHYPadsReducer: add Cat around Array (helps for standalone core integration).
2020-09-02 09:40:14 +02:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
9c5ce52b88
common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter.
2020-08-05 12:17:25 +02:00
805a37447c
Add support for TDQS mode.
...
This adds an optional argument to add_electrical_settings() that can
enable the TDQS mode for x8 DDR3 modules. Normally this would be used
when mixing x4 and x8 modules (eg: heterogenous DIMMS), but it can
also workaround boards with missing or broken DM signals.
2020-07-26 15:51:07 -07:00
639a31fdd2
test/test_timing: update test_txxd_controller.
2020-05-20 23:40:01 +02:00
3c1ab76bbc
litedram/common/tXXDController: only set reset to 1 when txxd is None.
...
This avoids triggering a warning/error with Yosys.
2020-05-19 13:10:32 +02:00
b2a5685396
Merge pull request #189 from daveshah1/ddr4_rdimm_init
...
Add support for DDR4 RDIMMs
2020-05-15 21:34:43 +02:00
5c0231d929
common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles.
2020-05-08 13:09:54 +02:00
70054bacdb
Add support for DDR4 RDIMMs
...
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:34:41 +01:00
9a2d3f0eb9
common: add PHYPadsReducer to only use specific DRAM modules.
...
For example on KC705, to only use the 4 first modules (bytes):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[0, 1, 2, 3])
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(ddram_pads,
[...]
On Arty, to only use the second module (byte):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[1])
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(ddram_pads,
[...]
2020-04-29 10:34:34 +02:00
48c2fc2cad
phy: simplify/improve dqs preamble/postamble.
...
Add some FIXMEs on ECP5DDRPHY.
2020-04-17 19:50:34 +02:00
62915cd777
phy: rework BitSlip to simplify integration, add DQSPattern module.
2020-04-16 17:13:37 +02:00
45a03dff53
phy/init: add phytype to PhySettings and export more parameters to C header to simplify software.
...
Also:
- rename some paramters exported to software.
- simplify wlevel registers on A7DDRPHY (add then even if not used).
- move parameters computation in separate section.
2020-04-16 10:20:34 +02:00
96b273c523
common/BitSlip: use reset_less on intermediate signal.
2020-04-06 11:59:34 +02:00
a04b407c81
common: PHYPadsCombiner: add "dqs" to the list
...
S6HalfRateDDRPHY uses "dqs" instead of "dqs_p"
2020-03-11 15:01:25 +01:00
5e068f412b
common: add PHYPadsCombiner to allow using fully dissociated DRAM chips and combine them to in single DRAM controller.
...
Most generally, DRAM chips are sharing command/address lines between chips (using a fly-by
topology since DDR3). On some boards, the DRAM chips are using separate command/address lines
and this combiner can be used to re-create a single pads structure (that will be compatible with
LiteDRAM's PHYs) to create a single DRAM controller from multiple fully dissociated DRAMs chips.
2020-03-06 18:46:07 +01:00
d646e2a6a7
common: add BitSlip module (with reduced latency)
2020-02-17 12:40:06 +01:00
aa1ce68896
global: improve presentation/readability
2019-11-30 10:53:11 +01:00
dc1bb53a88
phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common
2019-09-11 08:00:54 +02:00
188b6a8feb
add ZQ periodic short calibration support (default to 1s)
2019-09-09 15:07:38 +02:00
6e3f7691c5
core: move timing controllers to common
2019-07-23 12:39:14 +02:00
f018c9e268
add CONTRIBUTORS file and add copyright header to all files.
2019-06-23 23:59:10 +02:00
50e1d478db
PhySettings: add databits to allow SoC to compute memory size more easily
2019-05-10 15:44:44 +02:00
3caaa2eb13
common/tXXDController: revert Yosys workarounds
...
Now fixed with https://github.com/YosysHQ/yosys/pull/850
2019-04-29 14:24:31 +02:00
69afaf5a19
common: add separators, reorganize a bit
2019-03-15 20:08:08 +01:00
4274db809e
common/TXXDcontroller: fix for compatibility with Yosys and vendor tools
2019-03-04 12:48:42 +01:00
a74d5c9d9e
common/TXXDcontroller: set ready default value to 1 with self.comb instead of reset value
...
Fix SDRAM build with Yosys
2019-03-04 09:22:03 +01:00
224a423082
common: allow setting electrical settings with DDR4
2019-01-08 17:00:57 +01:00
af344897eb
common: add DDR4 burst_length
2018-11-05 10:46:34 +01:00
ab0d519ebb
core: change cba_shift parameter to more explicit address_mapping parameter
2018-10-19 17:38:04 +02:00
230ea24113
core: simplify/cleanup pass
2018-10-19 17:21:06 +02:00
167c0c91f6
remove partial reordering code in master, keep things in bank_reordering branch.
...
we'll try to stabilize master without reordering, then do some refactoring/adding a test suite to ease adding proper reordering later
2018-10-11 19:40:31 +02:00
bce411ec95
common: move tXXDController to common
2018-10-10 17:28:32 +02:00
208f5562d1
Merge branch 'master' of https://github.com/enjoy-digital/litedram
2018-10-01 19:36:05 -04:00
69eaf844e8
Fix DDR2 and below compilation failure
2018-10-01 19:35:20 -04:00
8de1d91eac
core: add with_bank paramteter to NativePort (cause issues on adaptation is bank is always exposed)
2018-10-01 11:18:39 +02:00
5984eaa6da
core: change api for out-of-order. (with_reordering passed to controller and not ports).
...
We are not going to mix in-order/out-of-order ports
2018-09-28 23:16:54 +02:00
Florent Kermarrec
Owen Kirby
David Shah
Mariusz Glebocki
John Sully