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1,110 Commits 5 Branches 14 Tags 5.7 MiB
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97 Commits

Author SHA1 Message Date
John Sully 177d7393f9 Implement tRAS 2018-09-23 19:42:46 +02:00
John Sully 5f6b85703d This adds support for tRC timing parameters 2018-09-23 17:56:07 +02:00
Florent Kermarrec f5c7b61704 multirank: set default nranks to 1 if not specified 2018-09-10 15:16:46 +02:00
Florent Kermarrec 8ddc6c735d drive odt of all ranks, fixes and test non regression with 1 rank 2018-09-09 01:52:24 +02:00
Florent Kermarrec b1c2739305 initial multirank support (nbankmachines = nranks * (2**bankbits)) 
To see:
Configure the 2 ranks. (init commands, leveling)
How to drive ODT?
Pipeline stall while switching ranks?
 2018-09-07 18:34:08 +02:00
Florent Kermarrec 9c729ae7b5 core: replace adr with addr on native interface (closer to AXI and allow some simplifications) 2018-08-29 17:06:03 +02:00
enjoy-digital cd330b4b44
Merge pull request #28 from AlphamaxMedia/refactor-master 
i think there's a missing "self" in the params
 2018-08-21 15:22:50 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
bunnie c9b8db5dc9 i think there's a missing "self" in the params 2018-08-21 17:28:42 +08:00
Florent Kermarrec 0b6e21ab6d improve ddr3 electrical settings 2018-08-21 10:45:42 +02:00
bunnie 697eaafc4c add board tuning parameters 2018-08-21 09:20:21 +02:00
03a2ad6bdc Ensure out of order is on a per-bank basis 2018-08-10 16:35:16 -04:00
86b3e2d2ef Add reorder flag to the crossbar 2018-08-10 15:54:22 -04:00
77c513d0f0 Merge upstream. UNTESTED 2018-08-10 00:31:00 -04:00
ed4be0b2a0 Add write bank to out of order interface 2018-08-10 00:20:13 -04:00
Florent Kermarrec f7f8452857 core: make rdata_bank optional (break cdc when enabled), fix some usecases 2018-08-09 10:54:30 +02:00
Florent Kermarrec 873b970fca frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup 2018-08-09 09:33:24 +02:00
2fa2a6d9f2 Initial implementation of out of order controller 2018-08-03 15:21:17 -04:00
f0f5e6036b Add tRRD timing checks, and fix tFAW so it considers all banks 2018-07-30 23:45:52 -04:00
Florent Kermarrec dec5378422 core/bankmachine: add CAS to CAS support (tCCD) 2018-07-13 15:03:04 +02:00
Florent Kermarrec 370b05ecf1 core/bankmachine: add Four Activate Window support (tFAW) 2018-07-09 17:27:58 +02:00
Florent Kermarrec 697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Florent Kermarrec abf028e0be global: reset_less optimizations 2017-07-01 11:18:05 +02:00
Florent Kermarrec 883e97101a common: add id to ports 2017-06-27 15:06:12 +02:00
Florent Kermarrec f57dfad6a4 frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter 2016-12-15 19:07:43 +01:00
Florent Kermarrec 5823373243 frontend: introduce mode on ports: write, read or both 2016-06-15 17:51:46 +02:00
Florent Kermarrec a016a820b5 common/LiteDRAMPort: add defaut cd value 2016-05-18 15:49:44 +02:00
Florent Kermarrec 8d066caea9 common: use cmd/wdata/rdata stream on LiteDRAMPort 2016-05-13 15:46:15 +02:00
Florent Kermarrec 30bacfeb1b frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests) 2016-05-13 15:27:12 +02:00
Florent Kermarrec 9d2c8bf1cf frontend: remove geom/timing parameters from LiteDRAMPort since this prevent providing async or arbitraty length port easily 2016-05-09 12:07:06 +02:00
Florent Kermarrec a40b0f760c test/bist_tb: cleanup and add error check 2016-05-03 22:22:11 +02:00
Florent Kermarrec 812d7dd7f0 frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
Florent Kermarrec 2709efa4a7 frontend/crossbar: remove controller_selected (no longer needed) 2016-05-03 17:11:34 +02:00
Florent Kermarrec e712a9d565 changes names on cmd_layout and data_layout 2016-05-03 17:02:59 +02:00
Florent Kermarrec 8c0e732c24 core: use a single structure to pass settings / simplify 2016-05-02 21:38:18 +02:00
Florent Kermarrec 7ce42d5324 bankmachine: rename fifo to cmd_buffer and allow depth < 2 (will be used to reduce logic when performance is not the priority) 2016-05-02 20:50:55 +02:00
Florent Kermarrec fb98d12241 only use positive logic in the controller(cas/ras/we) and use Record/stream.Endpoint for command requests 2016-05-02 12:18:56 +02:00
Florent Kermarrec cbe9748fa1 continue cleanup 2016-05-02 09:48:17 +02:00
Florent Kermarrec f37fc3d854 common: split Interface in InternalInterface/UserInterface 2016-05-02 09:20:12 +02:00
Florent Kermarrec 52a0f4e617 stb/req_ack becomes valid/ready + others small cleanup 2016-05-02 09:13:09 +02:00
Florent Kermarrec 1dac3fb7ba common: remove use of namedtuple (to improve readibility) 2016-04-29 19:22:06 +02:00
Florent Kermarrec 297c85d6cf move SDRAM modules in modules.py and others settings in common.py 2016-04-29 19:08:56 +02:00
Florent Kermarrec 997c1ce707 rename bus to common 2016-04-29 17:15:06 +02:00
Florent Kermarrec d48c298363 init from LiteX/MiSoC 2016-04-29 07:44:30 +02:00
Florent Kermarrec 0ef987dab1 bankmachine: some changes and first tests 2015-09-27 23:42:05 +02:00
Florent Kermarrec 7732ff27a6 update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
Florent Kermarrec 90595646f0 core / bankmachine / multiplexer skeleton 2015-02-22 21:59:48 +01:00