Commit Graph

176 Commits

Author SHA1 Message Date
Florent Kermarrec 17e228d4b0 phy/usrgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:24:35 +01:00
Florent Kermarrec 6270eb38d2 phy/s7rgmii: cleanup 2020-01-17 09:22:30 +01:00
Florent Kermarrec ee4f8c0f34 phy/usrgmii: improve presentation 2020-01-17 09:15:51 +01:00
Florent Kermarrec 2bdae4e7bd phy/s7rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:13:29 +01:00
Florent Kermarrec aea81e19e9 phy/s7rgmii: improve presentation 2020-01-17 09:05:09 +01:00
Florent Kermarrec 2748e442a9 phy/s6rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 09:03:34 +01:00
Florent Kermarrec 8fb0dae18a phy/s6rgmii: improve presentation 2020-01-17 08:57:52 +01:00
Florent Kermarrec 0cf9c2057d phy/ecp5rgmii: add configurable tx/rx_delay (2ns by default) 2020-01-17 08:54:31 +01:00
Florent Kermarrec e5c4ee7065 phy/ecp5rgmii: improve presentation 2020-01-17 08:35:15 +01:00
Florent Kermarrec 73bd27b506 phy/s7rgmii: add 2ns delay on ctl/data 2020-01-16 15:46:13 +01:00
Florent Kermarrec f2b3f7eeb1 test: update test_etherbone, use litex.gen.sim for all tests 2019-11-25 11:43:16 +01:00
Florent Kermarrec c71e42972a test: add test_examples (and remove test/Makefile) 2019-11-25 09:35:16 +01:00
Florent Kermarrec 10a911088c test: rename test_liteeth_gen to test_gen and call gen.py instead of liteeth_gen 2019-11-25 08:53:40 +01:00
Florent Kermarrec 6cce8c3c34 test: add test_liteeth_gen 2019-11-24 11:23:13 +01:00
Florent Kermarrec bb01840b12 add initial LiteEth standalone core generator from examples/core.py 2019-11-24 11:22:51 +01:00
Florent Kermarrec c1783ce554 examples/targets: update and cleanup 2019-11-23 19:49:23 +01:00
Florent Kermarrec d3b2f3d361 examples/targets: udpate analyzer 2019-11-23 15:47:42 +01:00
Florent Kermarrec dc8ddf6895 examples: keep up to date with LiteX 2019-11-23 15:23:24 +01:00
Florent Kermarrec 91f0f4ce80 test/model: improve presentation/readability 2019-11-23 15:17:22 +01:00
Florent Kermarrec 36c9951235 test: regroup model tests in test_model and run it with Travis-CI 2019-11-23 14:55:55 +01:00
Florent Kermarrec 7f31186b8c add Travis-CI 2019-11-23 00:16:01 +01:00
Florent Kermarrec bd1ead88d1 test: update for ci, for now disable test_etherbone since does not seem to finish 2019-11-23 00:14:19 +01:00
Florent Kermarrec 5a789570be mac/wishbone: remove FullMemoryWE (prevent simulation and should no longer be useful) 2019-11-23 00:12:46 +01:00
Vamsi K Vytla 57be29e68a global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links
To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle.
Pass dw to all modules to allow making use of it in the future. For now dw=8.
2019-11-21 11:01:55 +01:00
Florent Kermarrec ba83253ffa core/arp: fix typo 2019-11-21 11:01:53 +01:00
Florent Kermarrec 6b0a9251c0 global: keep up to date with LiteX (update stream_packet import to packet)
Retro-compatibily was ensure by LiteX but update it.
2019-11-21 11:01:50 +01:00
enjoy-digital 5bf218a00b
Merge pull request #23 from enjoy-digital/versa_ecp5_udp_loopback
Versa ecp5 udp loopback example
2019-11-20 09:44:15 +01:00
Florent Kermarrec e980b603cc example/udp_loopback: simplify/cleanup and make it more generic 2019-11-20 08:53:16 +01:00
Yehowshua Immanuel 50cc7d0671 examples: add practical UDP loopback example with Versa ECP5 2019-11-20 08:18:50 +01:00
Florent Kermarrec d2eb870445 core: allow passing ip_address as str 2019-11-07 13:23:10 +01:00
Florent Kermarrec 4d9e74f10a phy/usrgmii: cleanup (style, indent) 2019-09-28 22:16:07 +02:00
Florent Kermarrec 4bc79cefd8 examples/targets/core: update 2019-09-24 12:53:06 +02:00
enjoy-digital cd0eaa9607
Merge pull request #19 from jersey99/master
Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940
2019-09-05 11:07:59 +02:00
Vamsi K Vytla 59e04608a8 Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 2019-09-04 15:11:20 -07:00
Florent Kermarrec ad187d35f2 add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
Florent Kermarrec fd6d6c30ba mac: update imports 2019-06-24 11:23:13 +02:00
Florent Kermarrec a170acda0f change MAC location (next to phy/core/frontend), keep import retro-compatibility 2019-06-24 11:20:46 +02:00
Florent Kermarrec 789dadd8bf liteeth/software: remove libwip/libuip examples.
libuip integration can be found in https://github.com/timvideos/HDMI2USB-litex-firmware/tree/master/firmware
2019-06-17 21:17:52 +02:00
Florent Kermarrec 2424e62bf9 software: also include generated/mem.h 2019-05-20 09:00:25 +02:00
Florent Kermarrec e88fc507c8 software: remote ethmac_mem.h dependency (no longer exists in LiteX) 2019-05-19 19:29:04 +02:00
Florent Kermarrec b318300414 phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked 2019-04-11 21:51:09 +02:00
Florent Kermarrec e6c35cdec8 phy/ku_1000basex: incease pll_reset 2019-04-10 15:38:21 +02:00
Florent Kermarrec 816f592469 phy: add initial ECP5RGMII PHY 2019-02-25 14:45:19 +01:00
Florent Kermarrec b4c1cfe8c5 core/icmp: fix reply checksum when request checksum >= 0xf800
need to add +1
2019-02-24 23:30:46 +01:00
Florent Kermarrec 77fa4bfb1e phy: add Kintex7 1000BaseX PHY 2019-01-22 19:40:32 +01:00
Florent Kermarrec c2d8a467c9 phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) 2019-01-21 11:27:33 +01:00
Florent Kermarrec d7fdcbb1dc phy: add Spartan6 RGMII PHY 2018-12-18 08:58:16 +01:00
Florent Kermarrec 52c23015b0 frontend/etherbone: reduce default buffer_depth to 4 2018-10-30 11:21:06 +01:00
Florent Kermarrec 602ddec664 common: use reverse_bytes from litex.gen 2018-10-30 11:13:09 +01:00
Florent Kermarrec 40b99ecc05 test: use new RemoteClient import 2018-09-23 10:28:50 +02:00