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liteeth
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692 Commits 6 Branches 14 Tags 3.8 MiB
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692 Commits

Author SHA1 Message Date
Florent Kermarrec 4afd325fc6 core/dhcp: Shorten offered_ip_address to ip_address. 2023-07-03 18:06:48 +02:00
Florent Kermarrec 7a988bee22 core: Add initial/minimal DHCP support to hardware stack. 
Ex of use in a  SoC that issues a DHCP request per second:

from liteeth.core.dhcp import LiteEthDHCP

from migen.genlib.misc import WaitTimer

# Signals.
ip_address  = Signal(32)
mac_address = Signal(48, reset=0x10e2d5000001)

# Request Timer.
self.dhcp_timer = dhcp_timer = WaitTimer(int(sys_clk_freq/2))
self.comb += self.dhcp_timer.wait.eq(~self.dhcp_timer.done)

# DHCP.
dhcp_port = self.ethcore_etherbone.udp.crossbar.get_port(68, dw=32, cd="sys")
self.dhcp = dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=sys_clk_freq)
self.comb += [
    dhcp.start.eq(self.dhcp_timer.done),
    dhcp.mac_address.eq(mac_address),
]

self.sync += [
    If(dhcp.done,
        ip_address.eq(dhcp.offered_ip_address)
    )
]
 2023-07-03 17:44:48 +02:00
Florent Kermarrec ac4c2a7d44 liteeth/mac: Review/Minor changes to TXSlots write-only mode. 2023-07-03 10:50:07 +02:00
enjoy-digital 64627e3707
Merge pull request #135 from sensille/tx_write_only 
Tx write only
 2023-07-03 10:40:39 +02:00
Arne Jansen 53799444fd
Merge branch 'enjoy-digital:master' into tx_write_only 2023-06-28 18:50:48 +02:00
Florent Kermarrec 15054f6f8e liteeth_gen/sgmii: Expose link_up status. 2023-06-28 11:09:19 +02:00
Florent Kermarrec 18cd5f234a frontend/stream: Add 16-bit data-width support. 2023-06-28 11:02:37 +02:00
Arne Jansen e83fd55fe8 add tx_write_only flag 
This can save some resources in case reading the tx buffer is not needed.
It also makes it easier for synthesis to infer BRAM, tested on Spartan6.
 2023-06-27 16:35:50 +02:00
Florent Kermarrec 65ef1930f5 liteeth_gen: Add refclk_freq parameter for SGMII/1000BaseX. 2023-06-23 12:51:15 +02:00
Florent Kermarrec eab6b467f7 phy/usp_gtX_1000basex: Add 156.25MHz refclk_freq support in addition of 200MHz. 2023-06-23 12:43:35 +02:00
Florent Kermarrec 2dfd4398c9 phy/usp_gtX_1000basex: Use CPLLREFCLKSEL = 0b001 to let Vivado automatically select the right refclk. 2023-06-23 08:50:30 +02:00
Florent Kermarrec 2681a4f5d1 liteeth_gen: Finish adding Etherbone support. 2023-06-22 21:36:38 +02:00
Florent Kermarrec 52e94c02b5 liteeth_gen: Remove _eth suffix from PHY pads (not useful in case of a standalone core). 
Will however require an update from design using the standalone core.
 2023-06-22 17:31:01 +02:00
Florent Kermarrec 0d59ea180f examples: Add udp usp gth sgmii example. 2023-06-22 16:50:24 +02:00
Florent Kermarrec 4650cb0a01 liteeth_gen: Add SGMII PHYs support (7-Series and Ultrascale+). 2023-06-22 16:49:15 +02:00
Florent Kermarrec fc4003b115 liteth/phy: Update 1000basex imports and cleanup other imports. 2023-06-22 16:48:10 +02:00
Florent Kermarrec 9d22266233 frontend/stream: Update to LiteXModule and fix UDPTX packet send condition. 2023-06-14 11:17:37 +02:00
Florent Kermarrec 381ed30583 phy/k7_1000basex: Connect tx/rx_reset_done. 2023-06-13 19:18:29 +02:00
Florent Kermarrec 99d0fd92f3 phy/usp_gth_1000basex: Remove non-present/commented signals. 2023-06-13 19:13:40 +02:00
Florent Kermarrec 706f068822 phy/ku/usp_gth/gty_1000basex: Add rx/tx_polarity parameters for consistency with others 1000basex PHYs. 2023-06-13 19:12:04 +02:00
Florent Kermarrec 6c9dde1aca phy/ku/usp_gth/gty_1000basex: Add with_csr parameter for consistency with other 1000basex PHYs. 2023-06-13 19:08:24 +02:00
Florent Kermarrec 3e026795d8 bench/xcu1525/xu8_st1: Directly add IOs in Etherbone section. 2023-06-13 18:36:15 +02:00
Florent Kermarrec af5b9f433f README: Add PHY support/family table. 2023-06-13 18:09:15 +02:00
Florent Kermarrec 9f69850697 usp_gth_1000basex: Working :), remove debug. 2023-06-13 17:44:12 +02:00
Florent Kermarrec cfe3201854 phy/usp_gty_1000basex: Working :), remove debug. 2023-06-13 17:30:20 +02:00
Florent Kermarrec bea94efae1 bench: Add Mercury XU8/ST1 bench to test/validate USP_GTH_1000BASEX. 2023-06-13 16:46:49 +02:00
Florent Kermarrec d7aca70058 phy: Add initial usp_gth_1000basex (untested). 2023-06-13 16:41:26 +02:00
Florent Kermarrec 263eb1244f phy: Rename usp_1000basex to usp_gty_1000basex and update xcu1525. 2023-06-13 16:33:22 +02:00
Florent Kermarrec ee9d9e30e4 phy/1000basex: Move Gearbox to pcs_1000basex since common and rename it to PCSGearbox. 2023-06-13 16:27:14 +02:00
Florent Kermarrec be9f26e876 phy/k7_1000basex: Improve TX/RX init and add TX/RX polarity support. 2023-06-13 15:23:38 +02:00
Florent Kermarrec 5400515a1e phy/k7_1000basex: Replace specific TX/RX MMCM with S7MMCM. 2023-06-13 14:48:55 +02:00
Florent Kermarrec 9a67f4ea6b phy/a7_1000basex: Cleanup BUFH presentation. 2023-06-13 14:48:02 +02:00
Florent Kermarrec d63b340e34 bench: Add kc705 / K7_1000BASEX bench design. 2023-06-13 14:42:40 +02:00
Florent Kermarrec fa08ce1ccc bench: Update. 2023-06-13 14:13:03 +02:00
Florent Kermarrec 6d26f35ee4 phy/a7_1000basex: Make CSR optional (as done on k7_1000basex). 2023-06-13 13:56:18 +02:00
Florent Kermarrec e8efca804b phy/a7_1000basex: Replace specific TX/RX MMCM with S7MMCM. 2023-06-13 13:43:12 +02:00
Florent Kermarrec 5f2643ee83 phy/xgmii: Revert some changes since failing in CI. 2023-06-13 13:30:49 +02:00
Florent Kermarrec 5569cef1e2 phy/1000basex: Minor cleanups. 2023-06-13 10:42:40 +02:00
Florent Kermarrec 325f39b1cd phy/pcs_1000basex: stb/ack -> valid/ready. 2023-06-13 10:16:43 +02:00
Florent Kermarrec a9e41ef59b phy/pcs_1000basex: Minor changes/cleanups. 
- Switch to LiteXModule.
- Cosmetic cleanups for similarity with others modules.
- Use K/D definition from litex.soc.cores.code_8b10b.
 2023-06-13 10:13:32 +02:00
Florent Kermarrec 7046987ff1 phy/pcs_1000basex: Update from misoc. 2023-06-13 09:52:20 +02:00
Florent Kermarrec e9605ef9d8 phy/gmii/mii/rmii/xgmii: Switch to LiteXModule and minor simplifications/cleanups. 2023-06-13 09:35:17 +02:00
Florent Kermarrec 028838e744 phy/usp_1000basex: Update parameters from Xilinx PMA/PCS core. 2023-06-12 16:28:17 +02:00
Florent Kermarrec 150710d810 phy/usp_1000basex: Fix TX/RX_PROGDIV_CFG. 
TX and RX clks now up.
 2023-06-09 15:20:36 +02:00
Florent Kermarrec 8f7a1bf5d4 liteeth_gen: Disable wip Etherbone. 2023-06-09 08:32:42 +02:00
Florent Kermarrec 7f4df17615 liteeth_gen: Add initial (and wip) etherbone support. 2023-06-08 22:04:45 +02:00
Florent Kermarrec f00d95c534 usp_1000basex: Update a few parameter and add debug probes to investigate on xcu1525. 2023-06-08 17:56:37 +02:00
Florent Kermarrec a57178ac26 phy/rmii: Add with_refclk_ddr_ouptut parameter and minor cosmetic cleanups. 
Setting with_refclk_ddr_ouptut to False can allow use of RMII PHY on platforms
not supporting DDROutput.
 2023-05-24 19:18:53 +02:00
enjoy-digital bbed8f1c95
Merge pull request #133 from jersey99/usp-rgmii 
Make phy/usrgmii.py Ultrascale+ compatible
 2023-05-18 08:38:29 +02:00
Vamsi Vytla 7040b19937 make phy/usrgmii.py Ultrascale+ compatible 2023-05-17 14:56:20 -07:00