Commit Graph

542 Commits

Author SHA1 Message Date
Florent Kermarrec e0124748aa crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design. 2022-01-26 10:51:07 +01:00
Florent Kermarrec e340428384 liteeth_gen: Add configurable/dynamic MAC/IP address support. 2022-01-26 10:21:47 +01:00
Florent Kermarrec f264c9d5d5 liteeth_gen: Add toolchain support/parameter.
LiteX code specialization/generation can be different between toolchain (For the same vendor).
Add parameter to configure it from the .yml file.
2022-01-26 09:57:43 +01:00
Florent Kermarrec b38ca8d7c0 stream/LiteEthUDPStreamer: Add cd parameter. 2022-01-25 19:36:50 +01:00
Florent Kermarrec 14edaaeec2 frontend/stream: Add data_width support. 2022-01-14 18:38:21 +01:00
Florent Kermarrec 6a6bc28869 frontend/stream: Set sink.ready when udp_port or ip_address are invalid. 2022-01-14 18:02:53 +01:00
Florent Kermarrec 8faba46517 frontend/stream: Make ip_address filtering optional on LiteEthUDP2StreamRX. 2022-01-14 17:56:17 +01:00
enjoy-digital c3e3dee0e9
Merge pull request #100 from fjullien/fix_trionrgmii
phy: trionrgmii: add 'properties' to GPIO
2022-01-13 14:31:39 +01:00
Franck Jullien 31af9cabc2 phy: trionrgmii: add 'properties' to GPIO 2022-01-12 16:35:46 +01:00
Florent Kermarrec 561677634a Bump year. 2022-01-05 09:02:37 +01:00
enjoy-digital b317dc3558
Merge pull request #98 from yetifrisstlama/icmp
icmp: only send a ping reply to type 8 (ping request) packets
2022-01-05 08:35:20 +01:00
Michael Betz bc073a5d2c icmp.py: take icmp type field into account
* only send a ping reply to type 8 (ping request) packets
  * otherwise liteeth would send a ping reply to
    `destination unreachable` packets too, which is not wanted
2021-12-28 00:10:28 +01:00
Florent Kermarrec a8d9c5ef6a core/icmp: Revert to SyncFIFO for now until PacketFIFO regression is investigated. 2021-12-27 11:00:22 +01:00
enjoy-digital 7acb2a8c1c
Merge pull request #96 from lschuermann/dev/compliant-xgmii-fixup
phy/xgmii: remove vcd dump in test, fix comment
2021-11-21 21:19:17 +01:00
Leon Schuermann 4a0b6f736f phy/xgmii: fix description of IFG insertion
Fixes: ea0a65d357 ("phy/xgmii: handle IFG insertion ...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-21 19:31:07 +01:00
Leon Schuermann 6f0c1b6a91 test_xgmii_phy: remove vcd dump of XGMII test
Removes a slightly inappropriately named VCD dump created by the XGMII
tests which may or may not have been a result of some frustration
during the test implementation. :)

Fixes: 8da0423f64 ("Add XGMII PHY tests based on captured ...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-21 19:28:26 +01:00
enjoy-digital d9f19c60a8
Merge pull request #95 from lschuermann/dev/compliant-xgmii
phy/xgmii: handle IFG insertion in PHY, support deficit idle count
2021-11-21 19:16:49 +01:00
Leon Schuermann 8da0423f64 Add XGMII PHY tests based on captured CSV XGMII bus data
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:40:21 +01:00
Leon Schuermann 23ab5d2eb7 test_stream: allow premature stopping of the stream_collector
Support passing a stop_cond function which can cause the
stream_collector to exit on a user-defined condition.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:10:21 +01:00
Leon Schuermann ea0a65d357 phy/xgmii: handle IFG insertion in PHY, support deficit idle count
Because XGMII only allows start of frame characters to be placed on
lane 0 (first octet in a 32-bit XGMII bus word), when a packet's
length % 4 != 0, we can't transmit exactly 12 XGMII idle characters
inter-frame gap (the XGMII end of frame character counts towards the
inter-frame gap, while start of frame does not). Given we are required
to transmit a minimum of 12 bytes IFG, it's allowed to send packet
length % 4 bytes additional IFG bytes. However this would waste
precious bandwidth transmitting these characters.

Thus, 10Gbit/s Ethernet and above allow using the deficit idle count
mechanism. It allows to delete some idle characters, as long as an
average count of >= 12 bytes IFG is maintained. This is to be
implemented as a two bit counter as specified in IEEE802.3-2018,
section four, 46.3.1.4 Start control character alignment.

In practice, the previous implementation of the LiteEthPHYXGMIITX made
these issues even more prevalent: because the internal stream
interface is 64-bit wide and stream transactions always start aligned
to the first octet in a bus word, the previous primitive TX
implementation always started transmission on the first octet in the
64-bit XGMII bus word. The IFG inserter operated independently if the
PHY and thus made sure to maintain 12 bytes of IFG on the 64-bit
stream bus. This means that in a worst case scenario, the IFG could
grow to 23 octets. In applications such as Ethernet switches, the
consequences would be frequent buffer overruns or corrupt
transmissions.

Hence this commit introduces a IFG inserter in the LiteEthPHYXGMIITX
module itself. It is significantly more complex compared to the gap
inserter, but inserts the smallest legal gap as defined by
IEEE802.3. Furthermore, it optionally implements the deficit idle
count algorithm as described by Eric Lynskey of the UNH
InterOperability Lab1 to achieve an average IFG of 12 bytes.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-17 20:50:06 +01:00
Florent Kermarrec 1bbd90ae4d phy/trionrgmii: Fix source.last. 2021-11-16 18:50:04 +01:00
enjoy-digital 4dd95ea2a2
Merge pull request #94 from enjoy-digital/probe_fifo
frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation.
2021-11-09 11:35:27 +01:00
Florent Kermarrec 906208e16c phy: Add initial Efinix Trion RGMII PHY.
- Still experimenting a bit with Efinix Interface Writer/Peri.
- Still require adjusting TX/RX delays.
- Fixed TRIONPLL numbering.
- Etc...
2021-11-09 11:18:54 +01:00
Florent Kermarrec 491c5ab150 frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation.
Based on @Based on @david-sawatzke's analysis:
"Otherwise, depending on the caching in the path, a deadlock might occur due to the rx path being
blocked by the tx path, being blocked by the arp request, for which the answers get dropped in the
rx path."
2021-11-08 11:42:44 +01:00
enjoy-digital 20e0899109
Merge pull request #92 from david-sawatzke/dev/small_fixes
Small mac improvements
2021-11-08 10:33:47 +01:00
David Sawatzke f520751a69 mac/crc: Only output crc error on last word
Currently doesn't break anything, but it's a bit confusing while debugging
2021-11-06 15:54:04 +01:00
David Sawatzke 6b81121824 mac/core: Insert gap in phy tx cd
Otherwise if the sys cd is a bit too fast, the gap generated might get
eliminated by the cdc buffer
2021-11-06 15:54:04 +01:00
enjoy-digital 8ba5cf06a6
Merge pull request #90 from david-sawatzke/dev/hybridmac_8bit
mac/init: Add 32 & 64 bit support to hybrid mac (take two)
2021-11-04 14:59:10 +01:00
enjoy-digital b6c5e41097
Merge pull request #88 from lschuermann/dev/wtfverilog
{De,P}acketizer: fix source.last assignment between the two FSMs
2021-11-04 14:58:40 +01:00
David Sawatzke 3550f10fa3 mac: Extend hybrid mac to all dws and skip unneeded-conversion 2021-11-02 00:48:56 +01:00
Florent Kermarrec 9b03fc14de mac/sram: Properly fix length_lsb for dw==8 case. 2021-11-01 08:28:58 +01:00
Florent Kermarrec 2827e9947f mac/sram: Fix length_lsb slicing (+1). 2021-10-31 15:11:08 +01:00
Florent Kermarrec 1b25f7781c mac/sram: Add dw=8, 16 support and simplify logic (let the toolchain unused logic for 8/16/32-bit dw automatically). 2021-10-30 23:28:10 +02:00
Leon Schuermann 856062d9f0 {De,P}acketizer: fix source.last assignment between the two FSMs
This appears to fix some errors encountered during sending and
receiving of packets where sink.valid dropped to zero immediately
after last and the last_be overflowed onto the current bus word.

It turns out that the last_be FSM's changes to source.last are not
respected by the main FSM due to the way assignments to registers in
procedural blocks work on Verilog.

This introduces a selector for which last signal to use, goverened by
the last_be FSM.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
Co-authored-by: David Sawatzke <d-git@sawatzke.dev>
2021-10-28 15:35:12 +02:00
Florent Kermarrec 2ec2669f6b core/frontend/mac: Switch to local versions of Depacketizer/Packetizer. 2021-10-25 11:06:28 +02:00
Florent Kermarrec e11dbe8391 Create a local version of litex.soc.interconnect.packet to ease development of LiteEth specific Packetizer/Depacketizer's features.
Also move test_stream/test_packet.

This allow keeping last_be (that will be replaced in the future) self-contained to LiteEth and will
also simplify the rework on Packetizer/Depacketizer in LiteX, application in LitePCIe and
future rework/application in LiteEth.
2021-10-25 11:05:46 +02:00
enjoy-digital 2a5621474c
Merge pull request #85 from lschuermann/dev/mac-wishbone-dw
liteeth/mac: support SRAM/Wishbone operation with dw > 32 bit
2021-10-23 18:39:54 +02:00
enjoy-digital 9149524623
Merge pull request #84 from lschuermann/dev/core-arp-tx-last_be
core/arp: assert last_be only on the last data word
2021-10-23 18:38:01 +02:00
enjoy-digital 0944783984
Merge pull request #83 from david-sawatzke/dev/etherbone_last_be
frontend/etherbone: Add last_be everywhere
2021-10-23 18:36:55 +02:00
Leon Schuermann 359b024103 liteeth/mac: remove assertion of 32-bit dw for wishbone interface
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-10-13 17:51:23 +02:00
Leon Schuermann 540ad8c9dc liteeth/mac: use native dw for LiteEthMACWishboneInterface
This is required to support 64-bit wide data paths using the automatic
Wishbone bus width conversion as discussed in
enjoy-digital/liteeth#75. Otherwise, if the MAC data width deviates
from the 32-bit default set previously, received and transmitted
packets will be broken.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-10-13 17:47:28 +02:00
Leon Schuermann e663668717 core/arp: assert last_be only on the last data word
This is in line with other components of the LiteEth repository using
the `last_be` data qualifier. It is unexpected for last_be to be
asserted on any data word other than the last (i.e. only when `last`
is also asserted). In particular it can confuse the Packetizer and
cause it to pass through `last_be` on words other than the last as
well. This then irritates some parts of the MAC pipeline.

With these changes, ARP works on a 64-bit wide data path (with the
{Dep,P}acketizer changes integrated into LiteX).

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-10-13 17:43:53 +02:00
David Sawatzke f20432a2a5 frontend/etherbone: Add last_be everywhere
Needed for a full 32 bit path to work
2021-10-11 17:17:25 +02:00
Florent Kermarrec 8ecc3ca6d9 mac/core: Disable Preamble/CRC with LiteEthPHYModel. 2021-10-05 15:41:44 +02:00
Florent Kermarrec 5276a7543f mac/core: Split add_converter in add_cdc/add_converter/add_last_be. 2021-10-05 15:32:49 +02:00
Florent Kermarrec a4a070af4d mac/core: Introduce TX/RXDatapath modules to simplify code. 2021-10-05 15:13:08 +02:00
Florent Kermarrec 11555d43cb mac/core: Avoid passing core_dw/phy_dw to add_tx/rx_converter. 2021-10-05 14:20:22 +02:00
Florent Kermarrec 6204994bad common: Define eth_min_frame_length, eth_fcs_length and arp_min_length and use them in core/mac/model. 2021-10-05 14:10:41 +02:00
Florent Kermarrec 944849c3cf mac/core: Move CSRs to top and rename dw to datapath_dw. 2021-10-05 13:59:22 +02:00
Florent Kermarrec 821f725d58 mac/core: Improve modules's names: tx_xy/rx_xy everywhere. 2021-10-05 13:48:56 +02:00