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728 Commits

Author SHA1 Message Date
Florent Kermarrec a00640bf67 liteeth/mac/sram: Switch to LiteXModule. 2024-06-26 15:44:30 +02:00
enjoy-digital e4f5385ef1
Merge pull request #161 from enjoy-digital/wishbone_tx_rx_buses 
mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishb…
 2024-06-25 19:04:38 +02:00
Florent Kermarrec a118dd146f liteeth/gen: Update MACCore with EthMAC changes. 2024-06-25 18:53:46 +02:00
Florent Kermarrec 80bded4ffc liteeth/mac/wishbone: Fix write_only mode on RX. 2024-06-25 18:26:20 +02:00
Florent Kermarrec ec05e9c35c liteeth/mac/wishbone: Update copyrights. 2024-06-25 18:17:02 +02:00
Florent Kermarrec 0e3e645b44 test/test_mac_wishbone: Update with TX/RX slot changes. 2024-06-25 18:16:47 +02:00
Florent Kermarrec 591b77e991 mac/wishbone: Switch to LiteXModule. 2024-06-25 17:57:16 +02:00
Florent Kermarrec 20e892c214 mac/wishbone: Add _expose_wishbone_sram_interfaces to avoid duplicating code between TX and RX. 2024-06-25 17:56:12 +02:00
Florent Kermarrec 151b421a2c mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishbone buses to allow simultaneous TX/RX SRAM accesses. 
Useful in some designs to optimize throughput.
 2024-06-25 17:36:18 +02:00
Florent Kermarrec 7d24ac33ae version: Bump to 2024.04. 2024-06-05 22:07:12 +02:00
enjoy-digital e209a1c697
Merge pull request #160 from whiteb3ar/master 
phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed
 2024-04-14 08:26:23 +02:00
Andrei Novysh 0e8079a9da phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed 2024-04-14 00:37:31 +03:00
Florent Kermarrec a0d59dd264 frontend/stream/LiteEthStream2UDPTX: Condition source.last_be to source.last. 2024-04-11 10:47:02 +02:00
Florent Kermarrec 79ccffcfa7 mac/crc: Revert 30e66a7 (introducing a regression). 2024-04-08 17:51:53 +02:00
Florent Kermarrec 421e008fc8 mac/crc: Cosmetic cleanup. 2024-04-05 09:20:28 +02:00
Florent Kermarrec fb407ce98b core/ip/LiteEthIPTX: Enable buffer to ease timings on checksum. 2024-04-04 17:58:30 +02:00
Florent Kermarrec b5d7ba1220 core/udp: Revert TX/RX Buffer since not helping (at least for now). 2024-04-04 17:52:43 +02:00
Florent Kermarrec 211cdc26f3 core/ip: Add optional input buffer on LiteEthIPTX to improve timings. 2024-04-04 17:26:54 +02:00
Florent Kermarrec 30e66a7e21 mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output. 2024-04-04 16:39:32 +02:00
Florent Kermarrec 3e8103996f mac/crc/LiteEthMACCRC32Inserter: Switch crc_packet/last_be to reset_less for timings. 2024-04-04 16:17:36 +02:00
Florent Kermarrec b7443f5fd3 gen/mac: Allow 16-bit data_width. 2024-04-04 13:36:16 +02:00
Florent Kermarrec c18cfb8bc0 core/arp/LiteEthARPTX: Simplify last_be generation. 2024-04-04 13:35:57 +02:00
Florent Kermarrec d5ba0d21ef frontend/etherbone: Enable TX/RX buffer on UDP Port when requesting it (and others cosmetic cleanups). 2024-04-04 13:09:17 +02:00
Florent Kermarrec d558122251 core/udp: Allow adding TX/RX Buffer on interface to improve/cut timings. 2024-04-04 13:08:25 +02:00
Florent Kermarrec c250bb1485 mac/crc/LiteEthMACCRC32Inserter: Simplify crc.ce logic. 2024-04-04 13:06:59 +02:00
Florent Kermarrec 3c1f4dbf6c phy/a7_gtp: Allow using GTGREFCLK0/1 input as reference clocks. 
Useful when reference clock is generated from a PLL or MMCM.
 2024-04-04 10:50:47 +02:00
enjoy-digital c1dc02093d
Merge pull request #158 from enjoy-digital/crc_cleanup 
CRC cleanups.
 2024-03-26 12:41:30 +01:00
Florent Kermarrec bbdd6835aa mac/crc: Cleanup and try to move data-path connection outside of FSM for timings. 2024-03-26 11:55:13 +01:00
Florent Kermarrec b22ac619ab mac/crc: Avoid dummy CRC classes since we only have one CRC Engine implementation. 2024-03-26 11:36:43 +01:00
Florent Kermarrec 95ff76867f mac/crc: Rename dw to data_width. 2024-03-26 11:30:07 +01:00
Florent Kermarrec 01abb2a60f mac/crc/LiteEthMACCRC32: Rename last_be to be and add comments. 2024-03-26 11:28:09 +01:00
Florent Kermarrec 5fad30cbc9 mac/crc/LiteEthMACCRC32: Simplify last_be using reset value and merge for loops. 2024-03-26 11:07:06 +01:00
Florent Kermarrec d9f7ae4882 mac/crc: Another cleanup pass. 2024-03-26 10:50:49 +01:00
Florent Kermarrec aded91f8cb mac/crc: Add optmize_xors method and better signal names. 2024-03-26 10:25:22 +01:00
Florent Kermarrec 1720050729 mac/crc: Switch to LiteXModule, LiteX's Reduce and avoid OrderedDict (no longer required). 2024-03-26 09:59:22 +01:00
Florent Kermarrec 4af0c77371 phy/a7_1000basex: Switch txoutclk buffer to BUFG. 2024-03-25 16:00:39 +01:00
Florent Kermarrec 292551a0f1 phy/a7_1000basex: Add parameters to allow selecting TX/RX Clock Managment Modules (PLL or MMCM) and buffer types. 
This is useful when using multiple instance in the design to optimize/select resources and allow build.
 2024-03-22 12:28:24 +01:00
Florent Kermarrec 1a5d93509b liteeth_gen: Allow selection QPLL channel on Artix7 through qpll_channel parameter. 2024-03-19 17:56:13 +01:00
Florent Kermarrec 5eb986b004 liteeth_gen: Allow external QPLL on Artix7 to allow multiple PHYs per Quad. 
Requires setting qpll parameter to False in .yml config file.
 2024-03-18 14:24:32 +01:00
Florent Kermarrec 0914fb5e51 liteeth_gen: Add optional --name parameter to configure generated verilog name. 2024-03-18 13:49:45 +01:00
Florent Kermarrec 2c67d13456 examples: Improve identation/presentation. 2024-03-18 13:43:11 +01:00
Florent Kermarrec e3a5d6fc19 phy/pcs_1000basex: Expose timers to ease debug. 2024-03-04 16:19:08 +01:00
Florent Kermarrec ab4606c5a1 phy/1000basex: Expose pcs, tx_init and rx_init modules to ease debug. 2024-03-04 16:17:39 +01:00
Florent Kermarrec 3061bf91ce liteeth_gen: Make udp_ports definition optional in .yml file (ex for configuration with only Etherbone). 2024-02-29 14:56:52 +01:00
Florent Kermarrec 21ff1b9369 liteeth_gen: Remove unwanted data_width assertion on Etherbone. 2024-02-29 14:49:37 +01:00
Florent Kermarrec b4e2850623 phy/Ultrascale/1000BaseX: Configure PROGDIV_CFG from linerate. 2024-02-07 11:34:01 +01:00
Florent Kermarrec 80ba793bcf phy/Ultrascale/1000BaseX: Switch to LiteICLink's ChannelPLL for more flexibility/simplicity. 
LiteICLink's ChannelPLL directly computes the CPLL/DIV parameters.
 2024-02-07 09:24:01 +01:00
Florent Kermarrec 8f521d838c liteeth_gen: Finish Artix7 2500BaseX integration. 2024-02-06 18:26:54 +01:00
Florent Kermarrec 1fefe49e74 README: List 2500BaseX support. 2024-01-23 15:57:00 +01:00
Florent Kermarrec dd2ecfefd8 liteeth/phy: Add USP_GTY_2500BASEX support. 2024-01-23 15:55:25 +01:00