Florent Kermarrec
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ad9ecdbd5e
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use udp port 1234 for etherbone
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2017-06-22 11:28:45 +02:00 |
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Florent Kermarrec
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e68e2ed73c
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frontend/etherbone: add description
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2017-04-26 23:43:43 +02:00 |
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Florent Kermarrec
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f6d8ddbba0
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update litex uart
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2017-04-19 10:39:52 +02:00 |
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Florent Kermarrec
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62acb5df52
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example_designs: update
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2017-03-30 14:46:54 +02:00 |
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Florent Kermarrec
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42454a5448
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frontend/etherbone: add wishbone slave support (allow extending wishbone bridge over ethernet between boards)
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2017-03-30 14:46:30 +02:00 |
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Florent Kermarrec
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a067691222
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README: update
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2017-01-19 14:53:11 +01:00 |
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Florent Kermarrec
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c4856d1eb5
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test: start converting to python unittest
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2017-01-19 14:33:24 +01:00 |
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Florent Kermarrec
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e1da2df97d
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core/mac/sram: fix reception of frames larger than mtu
-use 32bits length CSR (allow software to detect frames larger than mtu)
-drop remaining bytes larger than mtu
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2016-05-01 07:37:24 +02:00 |
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Florent Kermarrec
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072969ff58
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common: fix eth_mtu (1530 bytes)
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2016-05-01 07:09:37 +02:00 |
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Florent Kermarrec
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94290016d0
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setup.py: fix version (0.1)
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2016-04-29 14:32:05 +02:00 |
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Florent Kermarrec
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33e36dc4d7
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use new Record.connect omit parameter (replace leave_out)
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2016-04-21 08:03:31 +02:00 |
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enjoy-digital
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8590310783
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Merge pull request #2 from mithro/master
Adding a .gitignore file.
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2016-04-19 06:07:22 +02:00 |
Tim 'mithro' Ansell
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2207cf3cc3
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Adding a .gitignore file.
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2016-04-19 13:02:12 +10:00 |
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Florent Kermarrec
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f55ce1aac6
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core/mac: simplify/improve performance of LiteEthMACSRAMReader
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
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2016-04-03 22:53:02 +02:00 |
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Florent Kermarrec
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c6875b7bff
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example_designs: use new litescope
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2016-03-31 21:27:08 +02:00 |
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Florent Kermarrec
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e006223fee
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test: fix model_tb
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2016-03-31 00:25:50 +02:00 |
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Florent Kermarrec
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de5410429b
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README: we are in 2016
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2016-03-31 00:06:08 +02:00 |
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Florent Kermarrec
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a189b2c195
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phy/s6rgmii: fix missing last signal
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2016-03-29 16:53:37 +02:00 |
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Florent Kermarrec
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b394f2f45e
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test/mac_wishbone_tb: fix simulation
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2016-03-25 12:26:02 +01:00 |
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Florent Kermarrec
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b7f3b3ef42
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test: finish etherbone_tb (simulator limitation removed)
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2016-03-23 09:48:02 +01:00 |
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Florent Kermarrec
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87924c84e6
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test: finish mac_wishbone_tb (simulator limitation removed)
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2016-03-23 09:47:47 +01:00 |
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Florent Kermarrec
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7ea1b5a22d
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test: use passive generators and some cleanup
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2016-03-23 01:42:35 +01:00 |
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Florent Kermarrec
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e73f35c733
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test: remove __init__.py and use setup.py develop
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2016-03-22 10:34:28 +01:00 |
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Florent Kermarrec
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2f15f3748e
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test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE)
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2016-03-21 19:59:29 +01:00 |
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Florent Kermarrec
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657ba4cb16
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global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
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2016-03-16 21:36:07 +01:00 |
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Florent Kermarrec
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9cd7dc3088
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global: use SyncFIFO instead of Buffer
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2016-03-16 19:45:43 +01:00 |
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Florent Kermarrec
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aff07c6809
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global: use new StrideConverter
|
2016-03-16 17:01:13 +01:00 |
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Florent Kermarrec
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51f56e79dd
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global: remove use of sop
|
2016-03-16 16:22:00 +01:00 |
|
Florent Kermarrec
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1f46aaeb55
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core/mac: remove frontend directory (too much directories) and some cleanup
|
2016-03-15 20:09:30 +01:00 |
|
Florent Kermarrec
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c3e15e7f7b
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core/mac: use fifo_depth of 64 for all phys
|
2016-03-15 19:41:53 +01:00 |
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Florent Kermarrec
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32243934fb
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global: use stream.Endpoint instead of Sink/Source (deprecated)
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2016-03-15 16:50:00 +01:00 |
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Florent Kermarrec
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9593e29756
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global: use 192.168.1.100 (remote)/ 192.168.1.50 (local) IP addresses
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2016-03-15 15:40:06 +01:00 |
|
Florent Kermarrec
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b7efe0fd46
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phy: remove pads_register parameter (does not save enough, priority to simplicity)
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2016-03-15 15:33:36 +01:00 |
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Florent Kermarrec
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5583fe5543
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phy/s6rgmii: RenameClockDomains --> ClockDomainsRenamer
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2016-02-24 23:51:31 +01:00 |
|
Florent Kermarrec
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1dae2b802c
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example_design/targets/core: cleanup
|
2016-02-10 10:50:38 +01:00 |
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Florent Kermarrec
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36399d65da
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example_designs/targets/core: add possibility to build udp cores (with hw udp/ip stack)
|
2016-02-10 10:29:23 +01:00 |
|
Florent Kermarrec
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fef1be9c35
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example_designs/targets: add Makefile to build cores
|
2016-02-10 10:27:11 +01:00 |
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Florent Kermarrec
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59bfdd3d7f
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example_design/targets/core: add RMII/GMII/RGMII support
|
2016-02-07 23:16:26 +01:00 |
|
Florent Kermarrec
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989ae268ec
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example_designs: add simple core generation example (MII / Wishbone)
|
2016-02-07 10:29:28 +01:00 |
|
Florent Kermarrec
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d38612db0c
|
remove use of Record.connect
|
2015-12-27 12:26:01 +01:00 |
|
Florent Kermarrec
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4cb6a20291
|
setup.py: exclude test directory
|
2015-12-19 21:06:15 +01:00 |
|
Florent Kermarrec
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b8b04ccc31
|
example_designs/make.py: do not use "-" in build_name
|
2015-12-12 16:49:48 +01:00 |
|
Florent Kermarrec
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1f19518d63
|
phy/common: add LiteEthPHYHWReset and use it on phys
|
2015-12-09 16:57:02 +01:00 |
|
Florent Kermarrec
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54d7c6620b
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phy: add mdio on all phys
|
2015-12-09 16:42:35 +01:00 |
|
Florent Kermarrec
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ad0b4a165f
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phy: rmii refactor (tested)
|
2015-12-07 15:46:15 +01:00 |
|
Florent Kermarrec
|
17ce01b58e
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core/mac/core: use fifo depth of 8 for RMII phy
|
2015-12-04 09:38:59 +01:00 |
|
Florent Kermarrec
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6006186fe0
|
phy/rmii: use 50MHz (instead of 100Mhz) and use DDROutput to generate ref_clk
|
2015-12-03 23:47:08 +01:00 |
|
Florent Kermarrec
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09e6b3a8d7
|
phy: add s7rgmii
|
2015-12-01 01:34:06 +01:00 |
|
Florent Kermarrec
|
6b39b0f674
|
phy: fix clock domains renaming (ClockDomainsRenamer refactoring issue)
|
2015-11-30 13:04:47 +01:00 |
|
Florent Kermarrec
|
133cb88ead
|
common: small cleanup
|
2015-11-27 19:51:26 +01:00 |