Commit Graph

466 Commits

Author SHA1 Message Date
Florent Kermarrec e2c1b81cd3 CONTRIBUTORS: Update. 2022-05-02 13:45:04 +02:00
Florent Kermarrec 6d71adae2b bench: Use full imports. 2022-05-02 13:09:28 +02:00
Florent Kermarrec d10cda84b6 core/LiteEthIPCore/LiteEthUDPIPCore: Expose with_sys_datapath parameter. 2022-04-25 17:48:54 +02:00
Florent Kermarrec 28c8871624 core/LiteEthIPCore/LiteEthUDPIPCore: Improve code readability. 2022-04-25 17:33:32 +02:00
enjoy-digital 2f6ac9a216
Merge pull request #105 from yetifrisstlama/master
packet.py: fix typo in Packetizer
2022-04-25 16:37:10 +02:00
enjoy-digital 678995c3cb
Merge pull request #97 from david-sawatzke/dev/liteethudprxfix
core/udp: Add dw>8 support to LiteEthUDPRX
2022-04-25 16:36:10 +02:00
Florent Kermarrec d20f36a6ba core/icmp/LiteEthICMPEcho: Revert to PacketFIFO now that issue is understood.
edd98c23cb
2022-04-25 15:55:59 +02:00
Florent Kermarrec 9c0a9659c1 bench/butterstick: Add JTAGBone and Analyzer in MAC/ARP/IP/UDP/Etherbone control path. 2022-04-25 15:38:55 +02:00
Florent Kermarrec 2a4d387563 bench: Add gsd_butterstick. 2022-04-25 14:26:43 +02:00
Michael Betz 5e4dd913fc packet.py: fix typo in Packetizer
* in some cases, the delayed sink data was updated even though
    sink was not valid, leading to corrupted source data
  * this broke etherbone reads with DW=64
2022-04-19 01:15:10 +02:00
Florent Kermarrec bc9162d578 frontend/etherbone: Add assert on buffer_depth to prevent miss-configuration. 2022-04-08 09:27:52 +02:00
Florent Kermarrec 4cd0a99187 phy/1000basex: Add crg_reset CSR for consistency with other PHYs. 2022-03-23 08:44:52 +01:00
Florent Kermarrec 9ab4419382 frontend/etherbone: Replace is by ==. (Reported by python3.8). 2022-03-16 16:46:37 +01:00
enjoy-digital 2eba4e6bbf
Merge pull request #102 from sergachev/master
phy/a7_1000basex: expose rx/tx polarity controls
2022-02-21 08:54:21 +01:00
Ilia Sergachev 4fdf0ea20e phy/a7_1000basex: expose rx/tx polarity controls 2022-02-20 18:25:23 +01:00
Florent Kermarrec d1d2ad4584 frontend/stream: Add with_broadcast parameter to allow broadcast reception (Enabled by default). 2022-02-16 14:13:54 +01:00
Florent Kermarrec dc96269c8f core/ip/tx: Add broadcast capability. 2022-02-16 14:12:46 +01:00
Florent Kermarrec aff1916a03 core/ip: Add with_broadcast parameter and set it to True by default (Allow IP broadcast reception). 2022-02-16 11:51:57 +01:00
David Sawatzke 72b1a1f91e core/udp: Add dw>8 support to LiteEthUDPRX
Pass through last_be or create a new one based on the length if needed

Initialize count at dw//8 and don't subtract source_length since it
could lead to underflow for very short packets. In case source.length is
not dw aligned, count will not be equal, so adjust comparison for that.

Crib last_be Case lookup from mac/sram.py
2022-02-04 17:16:20 +01:00
Florent Kermarrec b903b7257b frontend/stream: Switch FIFOs to buffered. 2022-02-03 15:58:06 +01:00
Florent Kermarrec 35b475727c frontend/stream/LiteEthStream2UDPTX: Fix length computation (depends on data_width). 2022-02-03 15:17:07 +01:00
Florent Kermarrec ba20fc7b71 liteeth_gen/udp: Improve flexibility and add support for multiple UDP virtual channels. 2022-01-28 10:11:45 +01:00
Florent Kermarrec 680806997d liteeth_gen/udp: Directly integrate UDPStreamer to simplify use and just expose a LiteX-Stream/AXI-ST interface. 2022-01-26 11:18:48 +01:00
Florent Kermarrec 2beec096b4 liteeth_gen: Move MAC/IP address configuration to Config section and add dynamic UDP port support. 2022-01-26 10:53:23 +01:00
Florent Kermarrec e0124748aa crossbar/LiteEthCrossbar: Allow dispatch_param to be a Signal to allow dynamic configuration from design. 2022-01-26 10:51:07 +01:00
Florent Kermarrec e340428384 liteeth_gen: Add configurable/dynamic MAC/IP address support. 2022-01-26 10:21:47 +01:00
Florent Kermarrec f264c9d5d5 liteeth_gen: Add toolchain support/parameter.
LiteX code specialization/generation can be different between toolchain (For the same vendor).
Add parameter to configure it from the .yml file.
2022-01-26 09:57:43 +01:00
Florent Kermarrec b38ca8d7c0 stream/LiteEthUDPStreamer: Add cd parameter. 2022-01-25 19:36:50 +01:00
Florent Kermarrec 14edaaeec2 frontend/stream: Add data_width support. 2022-01-14 18:38:21 +01:00
Florent Kermarrec 6a6bc28869 frontend/stream: Set sink.ready when udp_port or ip_address are invalid. 2022-01-14 18:02:53 +01:00
Florent Kermarrec 8faba46517 frontend/stream: Make ip_address filtering optional on LiteEthUDP2StreamRX. 2022-01-14 17:56:17 +01:00
enjoy-digital c3e3dee0e9
Merge pull request #100 from fjullien/fix_trionrgmii
phy: trionrgmii: add 'properties' to GPIO
2022-01-13 14:31:39 +01:00
Franck Jullien 31af9cabc2 phy: trionrgmii: add 'properties' to GPIO 2022-01-12 16:35:46 +01:00
Florent Kermarrec 561677634a Bump year. 2022-01-05 09:02:37 +01:00
enjoy-digital b317dc3558
Merge pull request #98 from yetifrisstlama/icmp
icmp: only send a ping reply to type 8 (ping request) packets
2022-01-05 08:35:20 +01:00
Michael Betz bc073a5d2c icmp.py: take icmp type field into account
* only send a ping reply to type 8 (ping request) packets
  * otherwise liteeth would send a ping reply to
    `destination unreachable` packets too, which is not wanted
2021-12-28 00:10:28 +01:00
Florent Kermarrec a8d9c5ef6a core/icmp: Revert to SyncFIFO for now until PacketFIFO regression is investigated. 2021-12-27 11:00:22 +01:00
enjoy-digital 7acb2a8c1c
Merge pull request #96 from lschuermann/dev/compliant-xgmii-fixup
phy/xgmii: remove vcd dump in test, fix comment
2021-11-21 21:19:17 +01:00
Leon Schuermann 4a0b6f736f phy/xgmii: fix description of IFG insertion
Fixes: ea0a65d357 ("phy/xgmii: handle IFG insertion ...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-21 19:31:07 +01:00
Leon Schuermann 6f0c1b6a91 test_xgmii_phy: remove vcd dump of XGMII test
Removes a slightly inappropriately named VCD dump created by the XGMII
tests which may or may not have been a result of some frustration
during the test implementation. :)

Fixes: 8da0423f64 ("Add XGMII PHY tests based on captured ...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-21 19:28:26 +01:00
enjoy-digital d9f19c60a8
Merge pull request #95 from lschuermann/dev/compliant-xgmii
phy/xgmii: handle IFG insertion in PHY, support deficit idle count
2021-11-21 19:16:49 +01:00
Leon Schuermann 8da0423f64 Add XGMII PHY tests based on captured CSV XGMII bus data
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:40:21 +01:00
Leon Schuermann 23ab5d2eb7 test_stream: allow premature stopping of the stream_collector
Support passing a stop_cond function which can cause the
stream_collector to exit on a user-defined condition.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-18 19:10:21 +01:00
Leon Schuermann ea0a65d357 phy/xgmii: handle IFG insertion in PHY, support deficit idle count
Because XGMII only allows start of frame characters to be placed on
lane 0 (first octet in a 32-bit XGMII bus word), when a packet's
length % 4 != 0, we can't transmit exactly 12 XGMII idle characters
inter-frame gap (the XGMII end of frame character counts towards the
inter-frame gap, while start of frame does not). Given we are required
to transmit a minimum of 12 bytes IFG, it's allowed to send packet
length % 4 bytes additional IFG bytes. However this would waste
precious bandwidth transmitting these characters.

Thus, 10Gbit/s Ethernet and above allow using the deficit idle count
mechanism. It allows to delete some idle characters, as long as an
average count of >= 12 bytes IFG is maintained. This is to be
implemented as a two bit counter as specified in IEEE802.3-2018,
section four, 46.3.1.4 Start control character alignment.

In practice, the previous implementation of the LiteEthPHYXGMIITX made
these issues even more prevalent: because the internal stream
interface is 64-bit wide and stream transactions always start aligned
to the first octet in a bus word, the previous primitive TX
implementation always started transmission on the first octet in the
64-bit XGMII bus word. The IFG inserter operated independently if the
PHY and thus made sure to maintain 12 bytes of IFG on the 64-bit
stream bus. This means that in a worst case scenario, the IFG could
grow to 23 octets. In applications such as Ethernet switches, the
consequences would be frequent buffer overruns or corrupt
transmissions.

Hence this commit introduces a IFG inserter in the LiteEthPHYXGMIITX
module itself. It is significantly more complex compared to the gap
inserter, but inserts the smallest legal gap as defined by
IEEE802.3. Furthermore, it optionally implements the deficit idle
count algorithm as described by Eric Lynskey of the UNH
InterOperability Lab1 to achieve an average IFG of 12 bytes.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-11-17 20:50:06 +01:00
Florent Kermarrec 1bbd90ae4d phy/trionrgmii: Fix source.last. 2021-11-16 18:50:04 +01:00
enjoy-digital 4dd95ea2a2
Merge pull request #94 from enjoy-digital/probe_fifo
frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation.
2021-11-09 11:35:27 +01:00
Florent Kermarrec 906208e16c phy: Add initial Efinix Trion RGMII PHY.
- Still experimenting a bit with Efinix Interface Writer/Peri.
- Still require adjusting TX/RX delays.
- Fixed TRIONPLL numbering.
- Etc...
2021-11-09 11:18:54 +01:00
Florent Kermarrec 491c5ab150 frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation.
Based on @Based on @david-sawatzke's analysis:
"Otherwise, depending on the caching in the path, a deadlock might occur due to the rx path being
blocked by the tx path, being blocked by the arp request, for which the answers get dropped in the
rx path."
2021-11-08 11:42:44 +01:00
enjoy-digital 20e0899109
Merge pull request #92 from david-sawatzke/dev/small_fixes
Small mac improvements
2021-11-08 10:33:47 +01:00
David Sawatzke f520751a69 mac/crc: Only output crc error on last word
Currently doesn't break anything, but it's a bit confusing while debugging
2021-11-06 15:54:04 +01:00