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926 Commits 9 Branches 14 Tags 11 MiB
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926 Commits

Author SHA1 Message Date
Florent Kermarrec 782c856619 platforms/genesys2: add usb_fifo. 2020-06-23 18:02:53 +02:00
Florent Kermarrec 936ba5b279 platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
Florent Kermarrec 55ed9fbf02 platforms/kcu105: add sdcard/spisdcard. 2020-06-23 11:44:40 +02:00
Florent Kermarrec eee00ebd0a platforms/genesys2: add sdcard/spisdcard. 2020-06-23 11:44:26 +02:00
Florent Kermarrec 6568c8a3ae platforms/netv2: add spisdcard. 2020-06-23 11:44:10 +02:00
Florent Kermarrec 7de7c4be5c platforms/kc705: rename mmc to sdcard and make it similar to other boards. 2020-06-23 10:56:31 +02:00
Florent Kermarrec 0ecb8609b3 platform/arty: also update spisdcard. 2020-06-16 20:15:12 +02:00
Florent Kermarrec 7a8b0b743d platforms/pano_logic_g2: -x. 2020-06-16 19:53:46 +02:00
enjoy-digital 2db7aa794f
Merge pull request #84 from antmicro/sdcard-pmod 
Change sdcard Pmod from JB to JD
 2020-06-16 19:47:51 +02:00
Kamil Rakoczy f70655d1ac Change sdcard Pmod from JB to JD 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2020-06-15 12:01:46 +02:00
Florent Kermarrec 04f6d4463a versa_ecp5: simplify device (LFE5UM5G or LFE5UM) and adapt integrated_rom_size only for Microwatt. 2020-06-13 11:17:05 +02:00
enjoy-digital 1537189594
Merge pull request #83 from madscientist159/master 
Fix Microwatt on Versa board
 2020-06-13 11:05:24 +02:00
Raptor Engineering Development Team 90092164c8 Add device option for ECP5 Versa board 
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
 2020-06-12 18:39:43 -05:00
Raptor Engineering Development Team b1be5dcc23 Fix FTBFS from undersized BIOS ROM region with Microwatt 
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
 2020-06-12 18:39:43 -05:00
Florent Kermarrec 9b45ec0f35 de10lite: simplify vga terminal. 2020-06-11 19:59:32 +02:00
Florent Kermarrec 85cac7abc0 de10nano/Mister: review/simplify. 2020-06-11 19:54:55 +02:00
Florent Kermarrec 64372d7876 targets/orangecrab: add spi-sdcard and workaround for ValentyUSB. 2020-06-11 19:21:44 +02:00
Florent Kermarrec c94cbae0c0 orangecrab: add user_led (RGB leds), DFUProg and --load support. 2020-06-11 19:21:40 +02:00
enjoy-digital 9aea2272eb
Merge pull request #80 from rob-ng15/master 
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board
 2020-06-11 18:16:18 +02:00
Florent Kermarrec 45bd50b000 targets: rename colorlight_5a_75b to colorlight_5a_75x (since we are now also supporting the 75e). 2020-06-10 23:14:37 +02:00
enjoy-digital ad1693a1ad
Merge pull request #82 from Disasm/colorlight-5a-75e 
Add Colorlight 5A-75E V7.1 board
 2020-06-10 23:09:26 +02:00
enjoy-digital b312c65eb9
Merge pull request #81 from Disasm/fix-5a-75b 
Update J4 pin 5 on Colorlight 5A-75B V7.0
 2020-06-10 23:07:33 +02:00
Florent Kermarrec 94861bbb9a targets/orangecrab: uncomment MT41K512M16. 2020-06-10 19:30:07 +02:00
Florent Kermarrec b6df166f5a platforms/arty: add spisdcard to _sdcard_pmod_io. 2020-06-10 17:38:16 +02:00
Florent Kermarrec 00c8e40d02 platforms/ulx3s: add sdcard pins. 2020-06-10 17:37:50 +02:00
Vadim Kaushan 0c590abf12
Update colorlight_5a_75b target: add 5A-75E board support 2020-06-10 03:20:32 +03:00
Vadim Kaushan 1acdb962a5
Add 5A-75E V7.1 board 2020-06-10 03:07:20 +03:00
Vadim Kaushan 939f05fea4
Update J4 pin 5 on Colorlight 5A-75B V7.0 2020-06-10 02:49:18 +03:00
rob-ng15 485c242f24
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board 2020-06-08 11:05:58 +01:00
rob-ng15 e52d6aca5f
Use 128mb sdram, uart via i/o port on i/o board and vga terminal via i/o board 2020-06-08 11:05:36 +01:00
enjoy-digital aa35cd2efb
Merge pull request #79 from gsomlo/gls-trellis-sdcard 
targets/trellisboard: add initial LiteSDCard support
 2020-06-03 19:57:05 +02:00
Gabriel Somlo f9a8edb973 targets/trellisboard: add initial LiteSDCard support 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-06-03 13:41:57 -04:00
Florent Kermarrec d87a11a9cb targets/pcie: use generate_litepcie_software on all targets with PCIe. 2020-06-03 08:30:54 +02:00
Florent Kermarrec 9f83b6e3cf targets/acorn_cle_215: use new generate_litepcie_software functions and add --driver argument to generate driver. 2020-06-03 08:20:43 +02:00
Florent Kermarrec 091ec846a1 targets/acorn_cle_215: automatically copy software from litepcie and generate headers in kernel directory. 2020-06-02 20:09:45 +02:00
Florent Kermarrec 06edf48897 targets: rename gateware-toolchain parameter to toolchain. 2020-06-02 13:45:05 +02:00
Florent Kermarrec 0b11aba8a1 platforms/nexys_video: add spisdcard pins. 2020-05-29 19:37:04 +02:00
Florent Kermarrec 76df4e39c8 targets: simplify Ethernet/Etherbone integration on targets with both. 2020-05-29 19:20:27 +02:00
Florent Kermarrec 2e1a816d1f pano_logic_g2: switch to LiteEthPHY and simplify Ethernet/Etherbone. 2020-05-29 10:41:35 +02:00
enjoy-digital 33fe308ef0
Merge pull request #78 from antmicro/jboc/spd-read 
ZCU104: add I2C
 2020-05-27 14:56:31 +02:00
Jędrzej Boczar e5578a1ae8 zcu104/platform: change I2C number to 0 2020-05-27 14:31:22 +02:00
Jędrzej Boczar ac1f1cd6a7 zcu104: add I2C 2020-05-27 12:47:43 +02:00
Florent Kermarrec 71f220a24d colorlight_5a_75b: remove unnecessary parenthesis. 2020-05-27 10:13:44 +02:00
Florent Kermarrec 2f3817cba9 pano_logic_g2: add ethernet (build but not functional yet) and use user_btn_n as sys_rst. 2020-05-27 10:13:12 +02:00
Florent Kermarrec f19bc36813 pano_logic_g2: add revision support (b and c, c as default) and add OpenOCD programmer. 
Tested with:
./pano_logic_g2.py --uart-name=jtag_uart --build --load
./litex_jtag_uart.py --config=openocd_xc6_ft232.cfg
lxterm /dev/pts/X
 2020-05-27 08:58:40 +02:00
Florent Kermarrec d6518c7dc2 prog/openocd: fix openocd_xc6 cfgs. 2020-05-27 08:48:16 +02:00
Florent Kermarrec 22f18f618e pano_logic_g2: move gmii_rst_n to _CRG. 2020-05-26 08:36:06 +02:00
enjoy-digital 935a71123b
Merge pull request #77 from skiphansen/master 
Take Ethernet PHY out of reset so default clock is 125 Mhz
 2020-05-26 08:28:29 +02:00
Skip Hansen 0648c04158 Updated comment, added link to clocking documentation. 2020-05-25 14:48:24 -07:00
Skip Hansen 1ab46562bd Take Ethernet PHY out of reset so default clock is 125 Mhz (and baud rate is 115,200) 2020-05-25 10:11:03 -07:00