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1144 Commits

Author SHA1 Message Date
Florent Kermarrec 4e03f66fad efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets. 
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
 2021-11-12 18:04:30 +01:00
Florent Kermarrec 77fffda9cd efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :) 2021-11-12 16:41:42 +01:00
Gwenhael Goavec-Merou 648d38da7e quicklogic_quickfeather: add button and GPIOIn 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2021-11-12 13:21:00 +01:00
Florent Kermarrec 5374c32873 test/test_targets: Exclude efinix_trion_t20_mipi_dev_kit from CI test. 2021-11-12 11:23:17 +01:00
Florent Kermarrec b6c5a85b98 Add initial Efinix Trion T20 MIPI Dev Kit support: CPU, ROM, RAM, UART and SPI Flash. 
Tested with:
./efinix_trion_t20_mipi_dev_kit.py --with-spi-flash --build --load
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov 12 2021 08:37:48
 BIOS CRC passed (2bec12a3)

 Migen git sha1: 7507a2b
 LiteX git sha1: f679992f

--=============== SoC ==================--
CPU:		VexRiscv @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32JV SPI Flash @0x00400000...
Enabling Quad mode...
First SPI Flash block erased, unable to perform freq test.
Memspeed at 0x400000 (Sequential, 4.0KiB)...
   Read speed: 2.6MiB/s
Memspeed at 0x400000 (Random, 4.0KiB)...
   Read speed: 1.5MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-11-12 08:42:10 +01:00
Florent Kermarrec d6fc4b412e efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied). 2021-11-12 07:58:51 +01:00
Florent Kermarrec 7ce8567d9b targets/efinix: Bitstreams now directly generated to gateware directory. 2021-11-11 11:19:39 +01:00
Florent Kermarrec 855fd7e3d7 efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration... 2021-11-10 19:40:35 +01:00
Florent Kermarrec 224f527baa efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration. 2021-11-10 12:07:30 +01:00
Gwenhael Goavec-Merou 040e7b3104 quicklogic_quickfeather: Use initial EOS-S3 support/integration. 2021-11-09 18:59:37 +01:00
Florent Kermarrec 8ce83ce92f efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working). 2021-11-09 16:13:40 +01:00
Florent Kermarrec 9a7e5f40b4 efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support. 
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
 2021-11-09 11:32:32 +01:00
Florent Kermarrec ccebae6f55 targets/hyperram: Update integration. 2021-11-08 16:39:49 +01:00
Florent Kermarrec 184f41e61a sipeed_tang_nano: Use PLL and 48MHz sys_clk, switch to SoCMini, add UARTBone (at 1MBauds). 
Working correctly on hardware with updated CH552 firmware & patched litex_server...
 2021-11-08 09:23:44 +01:00
enjoy-digital 63913d8c82
Merge pull request #292 from hansfbaier/master 
terasic_sockit now also can use the DRAM module from litedram
 2021-11-08 08:05:54 +01:00
Hans Baier 8124c51dd0
Merge branch 'litex-hub:master' into master 2021-11-08 12:48:23 +07:00
Hans Baier d6bf2fd00e terasic_sockit: Use standard SDRAM module from litedram 2021-11-08 12:48:03 +07:00
enjoy-digital 91d0cd50ea
Merge pull request #291 from sergachev/master 
sqrl_acorn: add vivado programmer option, fix warnings
 2021-11-07 22:14:11 +01:00
Ilia Sergachev 099d947a49 sqrl_acorn: fix vivado cfgbvs and config_voltage warnings 2021-11-07 16:18:22 +01:00
Ilia Sergachev 202b0e3e7d sqrl_acorn: add option to use vivado programmer 2021-11-07 16:18:00 +01:00
enjoy-digital 3dbad2ee06
Merge pull request #289 from hansfbaier/qmtech-altera-fixes 
QMTech Altera fixes
 2021-11-06 08:34:34 +01:00
Hans Baier f0356d8434 QMTech Daughterboard: remove xilinx specific attribute 2021-11-06 10:25:57 +07:00
Hans Baier a9847f15a7 qmtech_5cefa2: tuned the clock phase shift to be able to run the system at 105MHz 2021-11-06 09:58:10 +07:00
Hans Baier b2813cfb70 use the right DRAM chip for the QMTech Altera boards 2021-11-06 08:45:03 +07:00
Hans Baier ee5638a96b qmtech-boards: fix serial so that it gets replaced by daughterboard serial correctly 2021-11-06 06:49:25 +07:00
Florent Kermarrec 6e7c76b71e fairwaves_xtrx: Add clk60 (from USB PHY) as default Clk when no PCIe. 
Fixes CI.
 2021-11-05 15:22:55 +01:00
enjoy-digital ce229d60fb
Merge pull request #288 from litex-hub/fairwaves_xtrx 
Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1).
 2021-11-05 14:53:42 +01:00
Florent Kermarrec ceaaf67dfd Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1). 2021-11-05 14:52:45 +01:00
enjoy-digital 01463a81a4
Merge pull request #287 from hansfbaier/qmtech-fixes 
10cl006: add missing spiflash option
 2021-11-05 07:11:27 +01:00
enjoy-digital 4d99073ce3
Merge pull request #286 from hansfbaier/qmtech-5cefa2 
Add support for QMTech 5CEFA2 board (Cyclone V)
 2021-11-05 07:11:04 +01:00
Hans Baier 3a25af1c28 10cl006: add missing spiflash option 2021-11-05 09:57:04 +07:00
Hans Baier 0edce3a176 Add support for QMTech 5CEFA2 board (Cyclone V) 2021-11-05 09:53:25 +07:00
Florent Kermarrec a482d7f6de targets/qmtech_xc7a35t: Use gpio_serial as serial when not mounted on daughterboard. 2021-11-04 18:52:36 +01:00
Florent Kermarrec 9543b5efae marble/marble_mini: Add berkeleylab prefix. 2021-11-04 18:42:16 +01:00
Florent Kermarrec 5e5ae880a4 targets/litex_acorn_baseboard: Integrate WS2812/NeoPixel. 
Tested with:
./litex_acorn_baseboard.py --cpu-type=None --uart-name=uartbone --with-ws2812 --build --csr-csv=csr.csv --load
litex_server --uart --uart-port=/dev/ttyUSBX
And test script: https://gist.github.com/enjoy-digital/c32c679a9ee4429d7f38a5ca5016a45a
 2021-11-04 16:36:25 +01:00
enjoy-digital 808befec3b
Merge pull request #283 from yetifrisstlama/master 
add Marble-board platform and target file
 2021-11-04 15:20:11 +01:00
enjoy-digital a4f8f12067
Merge pull request #284 from hansfbaier/master 
QMTech boards: fix swapped RX/TX lines, remove double uart replacer
 2021-11-04 15:18:16 +01:00
enjoy-digital 2c2a6fe459
Merge pull request #285 from lapnd/master 
Use built-int RS232 port
 2021-11-04 15:17:30 +01:00
lapd d950b3feb5 Use built-int RS232 port 
Signed-off-by: lapd <lapd@soc.one>
 2021-11-03 22:50:40 +07:00
Hans Baier 7aa639ac0f QMTech boards: fix swapped RX/TX lines, remove double uart replacer 2021-11-02 09:34:25 +07:00
Michael Betz e645eb243b add marble board platform and target file 2021-10-28 18:41:22 +02:00
Florent Kermarrec 0c3f5b0fe1 prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone). 2021-10-27 17:27:07 +02:00
Florent Kermarrec 207afb98fc ego1: Switch to VideoTerminal (LiteVideo is no longer provided by default with LiteX). 2021-10-27 16:29:46 +02:00
Florent Kermarrec 91818bc5f0 targets/gsd_butterstick/BaseSoC: Set default device to 85F (consistency with default arguments). 2021-10-26 17:01:55 +02:00
Florent Kermarrec c7a91f9eab efinix: Enable identifier on SoC (issue fixed in LiteX). 2021-10-25 19:33:49 +02:00
Florent Kermarrec 4bcfde8882 efinix: Avoid no_we on ROM/RAMs (no longer required). 2021-10-25 19:10:03 +02:00
Florent Kermarrec d13a8d54b8 efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit. 
Now possible with recent LiteX changes to support Tristate IOs.
 2021-10-25 18:35:35 +02:00
Florent Kermarrec f230eaf9bc efinix_trion_t120_bga576: Add Tristate test code. 2021-10-25 15:01:34 +02:00
Florent Kermarrec 0ac0f9e75d efinix_xyloni_dev_kit: Switch to openFPGALoader to load bitstream. 2021-10-25 12:49:48 +02:00
Florent Kermarrec fc05379929 efinix_xyloni_dev_kit: Use PLL. 2021-10-25 12:16:47 +02:00