Commit Graph

1660 Commits

Author SHA1 Message Date
enjoy-digital 6c05ddae1b
Merge pull request #438 from shawnanastasio/nexys4_part_name
platforms/nexys4*: Update part name
2022-10-27 12:11:07 +02:00
enjoy-digital d863066942
Merge pull request #440 from jmrobles/main
Add FPGAWars Alhambra II
2022-10-27 09:29:14 +02:00
Chema f9d3a39001 chore fix target, args processing 2022-10-26 20:45:53 +02:00
Chema 189ee3de39 fix target 2022-10-26 20:36:18 +02:00
Chema 54af30a4be fix: arg cpu-variant 2022-10-26 20:23:14 +02:00
Chema 32be05cfb1 chore default CPU variant 2022-10-25 21:14:25 +02:00
Chema 125569b2cb add FPGAWars Alhambra II 2022-10-25 21:12:02 +02:00
Florent Kermarrec bd2f1c2553 targets/isx_im1283: Fix CI. 2022-10-22 16:23:50 +02:00
enjoy-digital 8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
enjoy-digital 474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
Shawn Anastasio d4b2461b5a platforms/nexys4*: Update part name
Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so
change it to xc7a100tcsg324-1 which works with both f4pga and Vivado.
2022-10-21 14:15:27 -05:00
Florent Kermarrec 5a8d846a86 targets: Remove add_csr calls (no longer required). 2022-10-21 08:42:24 +02:00
Florent Kermarrec 377cda05a3 ti60_f225_dev_kit: Switch 1.2V banks to 1.8V to fix compilation issues with latest Efinity.
Will need to be investigated more.
2022-10-20 18:21:52 +02:00
Gwenhael Goavec-Merou 4a5d5318d7 targets/redpitaya: fix csr & reset region 2022-10-20 16:35:57 +02:00
Florent Kermarrec fbfd457ea0 ci: Bump to ubuntu 20.04. 2022-10-14 18:16:28 +02:00
Icenowy Zheng 745ebbbfa1 Add ISX iM1283 board
ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.

This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
enjoy-digital cb65099399
Merge pull request #435 from trabucayre/fix_artyz7_build
targets/digilent_arty_z7: add flash region
2022-10-14 15:49:52 +02:00
Florent Kermarrec 23c6acd013 platforms/ti60_f225_dev_kit: Fix IO voltage conflicts between peripherals/banks.
Was already reported as a warning on 2021.1.165.2.19 but now an error with 2022.1.226.

Note: To get the build working with 2022.1.226 the following change had to be done to
pt/bin/writer/pinout.py, line 2254:
- table.add_rows(table_rows)
+ for table_row in table_rows:
+   table.add_row(table_row)
This would need to be investigated more to know if related to our local setup/machine.
2022-10-14 10:22:54 +02:00
Gwenhael Goavec-Merou e44e63f65d targets/digilent_arty_z7: add flash region 2022-10-13 19:48:41 +02:00
Florent Kermarrec 3b339ba9a3 platforms/xilinx_kc705: Fix flash proxy name. 2022-10-13 08:48:33 +02:00
Florent Kermarrec 99888c52ce xilinx_kc705/i2c: Add pullups. 2022-10-11 17:26:06 +02:00
enjoy-digital be8cd1f8a4
Merge pull request #432 from fjullien/add_qmtech_cyclone_4_starter_kit
Add qmtech Cyclone IV Starter Kit
2022-10-10 09:25:42 +02:00
Franck Jullien 3ec18c3583 Add qmtech Cyclone IV Starter Kit 2022-10-09 16:34:44 +02:00
Florent Kermarrec e6762e228c targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI). 2022-10-04 09:45:51 +02:00
Florent Kermarrec d0dd009329 targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch). 2022-10-04 09:29:59 +02:00
enjoy-digital d6dadb6058
Merge pull request #431 from mntmn/master
MNT RKX7: update platform and target for D-2 release
2022-10-04 08:57:24 +02:00
Lukas F. Hartmann c38b8b1d8c MNT RKX7: update platform and target for D-2 release 2022-10-03 20:09:48 +02:00
enjoy-digital bece3b67aa
Merge pull request #430 from pftbest/ddr_fix
stlv7325: Adjust DDR3 pins to match the reference design
2022-10-01 13:50:21 +02:00
Vadzim Dambrouski cf416d0d66 stlv7325: Adjust DDR3 pins to match reference design 2022-10-01 11:15:47 +02:00
enjoy-digital fb6efe1fa2
Merge pull request #429 from trabucayre/video_swap_blue_red
targets/litex_acorn_baseboard: fix pn_swap
2022-09-29 17:04:52 +02:00
Gwenhael Goavec-Merou 85ba931a3d targets/litex_acorn_baseboard: fix pn_swap 2022-09-28 21:17:16 +02:00
enjoy-digital 2bc3049690
Merge pull request #427 from pftbest/patch-1
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute
2022-09-27 10:18:21 +02:00
Vadzim Dambrouski 57eb907210
aliexpress_stlv7325: Fix missing parameter for PULLUP attribute 2022-09-25 23:13:44 +02:00
Florent Kermarrec 8c3a5c0608 sipeed_tang_nano_9k: Fix HDMI IOs constraints. 2022-09-23 11:18:30 +02:00
Florent Kermarrec 9cd1c1cbd5 targets/digilent_arty: Switch with_buttons to False by default (To fix #426). 2022-09-23 10:07:17 +02:00
enjoy-digital dcb9e2b763
Merge pull request #424 from slagernate/main
add option to use ecpprog for crosslink-nx eval board
2022-09-19 13:33:48 +02:00
slagernate 9dbee62eac add option to use ecpprog for crosslink-nx eval board 2022-09-15 12:27:08 -07:00
Florent Kermarrec 30180892fa test/test_targets: Exclude newae_cw305 from platform tests. 2022-09-13 14:55:24 +02:00
Florent Kermarrec 3cef11e04d platforms/newae_cw305: Add sma_clk_in/out, buttons, switches and expansion header connector. 2022-09-13 14:26:52 +02:00
Florent Kermarrec f1899954e9 Add initial NewAE CW305 board support. 2022-09-13 12:38:30 +02:00
enjoy-digital 7b2e94b01f
Merge pull request #422 from azzeloof/master
Adding DFU Support to the Butterstick Platform
2022-09-12 09:04:29 +02:00
Adam Zeloof 25c28d2c03 fixed issue with default programmer option 2022-09-10 18:16:04 +01:00
Adam Zeloof 6768be7f66 changed use example comment 2022-09-10 17:56:02 +01:00
Adam Zeloof e8504191e3 cleanup 2022-09-10 17:54:43 +01:00
Adam Zeloof 6d0a4c788e Added DFU support to Butterstick 2022-09-10 17:45:57 +01:00
Florent Kermarrec 756e4f73fc sipeed_tang_primer_20k: Cleanup CRG. 2022-09-08 17:27:41 +02:00
Florent Kermarrec fadc5619f1 sipeed_tang_primer_20k/ddr3: Add litescope debug. 2022-09-07 17:46:46 +02:00
Florent Kermarrec 6c7157f799 sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status. 2022-09-07 17:07:07 +02:00
Florent Kermarrec d39d87b701 sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules. 2022-09-07 12:06:22 +02:00
Icenowy Zheng 1663ded641 sipeed_tang_primer_20k: Add initial DDR3 integration (WIP). 2022-09-07 11:53:24 +02:00