33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
60b769b624
efinix_trion_t120_bga576_dev_kit/ethernet: Disable software debug (RX now seems to be working fine).
2021-11-16 18:53:15 +01:00
996f5b2edd
efinix_trion_t120_bga576_dev_kit: Enable target1 port and also connect it to SoC.
2021-11-16 18:12:42 +01:00
7ce6c4cf79
efinix_trion_t120_bga576_dev_kit: Switch to ctrl_type = "none" (Also seems to work fine, avoid ddr_reset_sequencer dependency).
2021-11-16 17:50:47 +01:00
99f4f97f00
efinix_trion_t120_bga576_dev_kit: Use new InterfaceWriterBlock/InterfaceWriterXMLBlock and move PLL/DRAM blocks definition to target.
2021-11-16 17:41:26 +01:00
06bae58f48
efinix_trion_t120_bga576: Do a bit a of cleanup on LPDDR3 now that working.
2021-11-12 19:43:28 +01:00
86f6d7e66b
efinix_trion_t120_bga576_dev_kit: Remove test command.
2021-11-12 18:06:11 +01:00
4e03f66fad
efinix_trion_t120_bga576_dev_kit: Remove debug, integrate LPDDR3 as done on other targets.
...
Also lower sys_clk_freq since seems to cause issue with DRAM at 100MHz: Needs to be investigated.
2021-11-12 18:04:30 +01:00
77fffda9cd
efinix_trion_t120_bga576_dev_kit: Switch to UARTBone, Add LiteScope on Pseudo-AXI, fix addressing and do first successful LPDDR3 accesses :)
2021-11-12 16:41:42 +01:00
d6fc4b412e
efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).
2021-11-12 07:58:51 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
855fd7e3d7
efinix_trion_t120_bga576_dev_kit: Continue LPDDR3 integration...
2021-11-10 19:40:35 +01:00
224f527baa
efinix_trion_t120_bga576_dev_kit: Go a bit further in DRAM integration.
2021-11-10 12:07:30 +01:00
8ce83ce92f
efinix_trion_t120_bga576_dev_kit: Add inital LPDDR3 integration (not yet working).
2021-11-09 16:13:40 +01:00
9a7e5f40b4
efinix_trion_t120_bga576_dev_kit: Add Ethernet/Etherbone support.
...
Still not fully validated: TX seems OK but RX seems shifted/corrupted.
2021-11-09 11:32:32 +01:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
...
Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
f230eaf9bc
efinix_trion_t120_bga576: Add Tristate test code.
2021-10-25 15:01:34 +02:00
914e330a86
efinix_trion_t120_bga576_dev_kit: Add Flash support (Through openFPGALoader).
2021-10-15 09:38:43 +02:00
195bf176cf
efinix_trion_t120_bga576: Add SPIFlash support (X1 for now).
2021-10-14 19:16:01 +02:00
03c34e31cd
efinix_trion_t120_bga576: Add PLL to CRG and increase default sys_clk to 100MHz.
2021-10-14 15:45:26 +02:00
2ea803b7d1
efinix_trion_t120_bga576: Set no_we on integrated_main_ram.
...
To allow --integrated-main-ram-size use.
2021-10-14 10:19:18 +02:00
430918756d
efinix_trion_t120_bga576: Add PMODs connectors and use USB-UART/PMOD_E as Serial.
2021-10-14 10:10:42 +02:00
36897f4646
efinix_trion_t120_bga576: Disable Identifier (crashes design) and move no_we, working.
...
./efinix_trion_t120_bga576_dev_kit.py --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS CRC passed (b23a7321)
Migen git sha1: 7507a2b
LiteX git sha1: 8316fbf1
--=============== SoC ==================--
CPU: VexRiscv @ 40MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-10-14 09:39:54 +02:00
ad773b6f2f
efinix_trion_t120_bga576: Fix argparse description.
2021-10-13 17:28:43 +02:00
6c17d76a92
targets/efinix_trion_t120_bga576: Switch to SoCCore (with CPU) and use button as reset (and AsyncResetSynchronizer).
2021-10-13 16:35:14 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou