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19 Commits

Author SHA1 Message Date
Josuah Demangeon 538399cb3b lattice_ecp5_evn: update OpenOCD syntax 
When running `litex_server`, this error appeared:

    can't read "_CHIPNAME": no such variable

This is a fix for the specific lattice_ecp5_evn board.
It also refreshes the OpenOCD syntax.
 2023-07-31 14:05:34 +02:00
AEW2015 e20391d366 Basic SoC for Opal Kelly XEM8320 2023-02-28 13:19:12 -07:00
Florent Kermarrec 0ce7f8354c Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)). 
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  3 2022 18:59:46
 BIOS CRC passed (5f29afcc)

 LiteX git sha1: a4cc859d

--=============== SoC ==================--
CPU:		VexRiscv @ 80MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
 2022-05-03 19:04:06 +02:00
Ilia Sergachev 5cd1d7eaec add openocd config for litex acorn baseboard 2022-02-13 16:44:40 +01:00
Jevin Sweval 9e5224ca49 Add JTAGbone support to Terasic DECA 
Along the way I added UARTbone support to DECA as well for debugging.

Examples:

./terasic_deca.py --csr-csv csr.csv --with-jtagbone --build --load
litex_server --jtag --jtag-config ../prog/openocd_max10_blaster2.cfg
litex_term crossover

./terasic_deca.py --csr-csv csr.csv --uart-name jtag_uart --build --load
litex_term --jtag-config ../prog/openocd_max10_blaster2.cfg jtag
 2022-01-27 14:13:58 -08:00
Florent Kermarrec 0c3f5b0fe1 prog/openocd_butterstick: Set _CHIPNAME to ecp5 (for jtag_uart/jtag_bone). 2021-10-27 17:27:07 +02:00
Florent Kermarrec 1f149ece6b Add intial ButterStick support (with just Clk, Buttons and Leds). 2021-09-01 17:33:54 +02:00
Jędrzej Boczar a834985e00 Add target for LPDDR4 Test Board 2021-03-30 14:50:02 +02:00
Gary Wong 4e5bb1bf1e Add FPC-III board support. 
FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
 2021-01-28 09:51:42 -07:00
Guillaume REMBERT 9beba7209d Add ECPIX5 components and pinouts (pmod/sata/spiflash) + review IDs from ECPIX5 openocd configuration 2021-01-28 12:00:28 +01:00
Florent Kermarrec d18deef10d colorlight_5a_75x: switch prog to FT232 based programmer (ex: JTAG HS2). 2020-11-23 10:13:57 +01:00
Florent Kermarrec 936ba5b279 platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
Florent Kermarrec d6518c7dc2 prog/openocd: fix openocd_xc6 cfgs. 2020-05-27 08:48:16 +02:00
Florent Kermarrec 445338e2e7 platforms/nexys_video: add specific openocd cfg (use channel 1). 2020-05-22 14:12:45 +02:00
Vamsi K Vytla e4ccfcfad1 platforms/marblemini.py: Cleanup. Add openocd for programming marblemini 2020-05-08 17:20:14 -07:00
Florent Kermarrec d34c3baf15 prog: use different openocd config files for FT232/FT2232. 2020-05-06 16:14:51 +02:00
Florent Kermarrec 117d1a1c75 prog: add colorlight_5a_75b openocd config. 2020-05-06 16:01:59 +02:00
Florent Kermarrec 19eb5708de platforms: make sure all traditional platforms have a create_programmer method. 2020-05-05 13:34:57 +02:00
Florent Kermarrec 588bbac719 add prog directory with some Xilinx OpenOCD configurations files. 2020-05-05 09:11:06 +02:00