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2082 Commits

Author SHA1 Message Date
Greg Davill 59a897e2dd
gsd_butterstick: Add missing pin defs 2023-01-16 17:32:39 +10:30
Hans Baier c0773ed9b9 HPC FPGA Store on AliExpress renamed itself to SITLINV 2023-01-16 11:31:35 +07:00
Florent Kermarrec 36a4100c8b ocp_timecard: Add DDR3 SDRAM support. 2023-01-13 12:41:34 +01:00
Florent Kermarrec 3ca298ba42 ocp_tap_timecard: Add TODO on SMAs. 2023-01-13 11:51:09 +01:00
Florent Kermarrec c753bf7fc1 ocp_tap_timecard: Fix GTPE2 location. 2023-01-13 11:47:52 +01:00
Florent Kermarrec 8b0d4787c7 ocp_tap_timecard: Fix CI. 2023-01-13 10:55:07 +01:00
Florent Kermarrec 1e35d78512 ocp_tap_timecard: Add initial SMAIOs peripherals to allow using SMA over PCIe DMA or also with direct (and slow) control/visualization with CSR registers. 2023-01-13 10:08:44 +01:00
Florent Kermarrec fc7154a632 ocp_tap_timecard: Add Leds/I2C/PMOD/GPS/SMAs IOs. 2023-01-13 09:14:05 +01:00
Florent Kermarrec a0fd3e7536 Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested). 2023-01-12 18:50:23 +01:00
enjoy-digital 3ca0c7a035
Merge pull request #467 from mlaga97/master 
Allow building digilent_arty using f4pga
 2023-01-07 09:49:31 +01:00
Luc Lagarde 7a911b8ff6
Allow building digilent_arty using f4pga 
Only use XADC() and DNA() functions if vivado is the current toolchain.
 2023-01-06 16:09:56 -06:00
enjoy-digital 6658f20682
Merge pull request #465 from gatecat/vip-fix 
nx_vip: Add missing 'origin' to SRAM SocRegions
 2023-01-04 19:51:11 +01:00
gatecat 764f64ff1e nx_vip: Add missing 'origin' to SRAM SocRegions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-04 12:02:11 +01:00
Florent Kermarrec f5643e7c78 machdyne: Fix LiteDRAM PHYs imports (QuarterRateGENSDRPHY not already working?/integrated). 2023-01-01 21:35:51 +01:00
enjoy-digital 563ccbd8cf
Merge pull request #464 from machdyne/master 
initial support for machdyne konfekt and noir
 2023-01-01 16:12:51 +01:00
enjoy-digital 5de6865cbe
Merge pull request #463 from stone3311/master 
terasic_deca: add SPI SD card support
 2023-01-01 16:10:30 +01:00
enjoy-digital 798faa18df
Merge pull request #462 from jiv4ik/Tang_primer_20K_3690-Dock_3709 
Correct pinout and IOStandard
 2023-01-01 16:09:09 +01:00
inc fec82c59e2 remove konfekt ethernet option 2022-12-30 17:36:52 +01:00
inc f0dc9a6874 initial support for machdyne konfekt and noir 2022-12-30 17:00:35 +01:00
stone3311 6cfb56bb07 terasic_deca: add SPI SD card support 2022-12-28 02:13:06 +01:00
jiv4ik 57845d1ca4
Correct pinout and IOStandard 
Correct connector pinout
Correct pinout for ETH
LED IOStandard set to LVCMOS33
BTN[0] IOStandard set to LVCMOS33
Changes are made based on Tang_primer_20K_3690 and Tang_Primer_20K-Dock_3709 schemes.
 2022-12-22 18:30:36 +03:00
Gwenhael Goavec-Merou 4e06e5ff9c targets/xilinx_zybo_z7: adding missing variant parameter to the platform 2022-12-14 07:47:09 +01:00
Gwenhael Goavec-Merou a92fdffb35 platforms/digilent_zybo_z7: reorder _io_x & _connectors_x, init cleanup 2022-12-12 22:17:39 +01:00
JoyBed d28894a4b3
Reintroduce original Zybo + HDMI addition (#461) 
* Reintroduce original Zybo support

* Reintroduce original zybo, add HDMI + fixes for Z7
 2022-12-12 22:05:47 +01:00
Florent Kermarrec 12db52471d targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash). 2022-12-08 08:37:13 +01:00
enjoy-digital c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config 
Arty z7 tcl config
 2022-12-08 08:31:22 +01:00
enjoy-digital 71f1e1976b
Merge pull request #459 from tcal-x/icebitsy-ledchaser 
Add LedChaser to iCEBreaker-bitsy.
 2022-12-06 09:05:37 +01:00
enjoy-digital 8712606d6d
Merge pull request #455 from guissalustiano/master 
fix: Basys3 V_sync is pin R19
 2022-12-06 09:04:45 +01:00
Guilherme Salustiano 25c40ddda7 add gpio to board 2022-12-05 21:38:56 -03:00
Tim Callahan 6e205be83b Add LedChaser to iCEBreaker-bitsy. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2022-12-04 17:58:20 -08:00
Gwenhael Goavec-Merou a889321535 targets/digilent_arty_z7: adding note to load gateware and bios 2022-12-03 16:54:52 +01:00
Gwenhael Goavec-Merou e71e3ab3ec platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration 2022-12-03 16:54:39 +01:00
Guilherme Salustiano d0d90e9eef
Merge branch 'litex-hub:master' into master 2022-11-29 15:25:41 -03:00
Gwenhael Goavec-Merou b030630237
Merge pull request #453 from cklarhorst/zybo 
Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
 2022-11-25 21:48:43 +01:00
mkuhn99 53b6bf035a fixed parser 2022-11-24 16:03:12 +01:00
mkuhn99 926ed21f0b fixed review remarks; added zynq7000 as a submodule for using the ps as a slave 2022-11-23 17:20:25 +01:00
Guilherme Salustiano 570ea11744
fix(plataform.basys_3): V_sync is pin R19 
Based in https://github.com/Digilent/digilent-xdc/blob/master/Basys-3-Master.xdc#LL129C34-L129C37
 2022-11-23 09:16:50 -03:00
enjoy-digital 888b52d838
Merge pull request #452 from Icenowy/im1283-enh 
Some small enhancements to iSX iM1283
 2022-11-22 16:11:02 +01:00
mkuhn99 c489347a51 fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC 2022-11-18 11:19:57 +01:00
mkuhn99 6f7716adbb added config for ps7; introduced different variants for the zybo-board; fixed pins 2022-11-18 11:15:54 +01:00
Icenowy Zheng 892bf3546d isx_im1283: connect CRG reset to PLL 
This fixes soft reset.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-16 15:12:18 +08:00
Icenowy Zheng e27d8c958e isx_im1283: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-15 21:07:10 +08:00
Florent Kermarrec ae47172d2a targets/decklink_mini_4k: Update clock constraints. 2022-11-14 10:21:42 +01:00
Florent Kermarrec 6e10df234f platforms/decklink_mini_4k: Fix data2_n pin (Thanks @rdolbeau). 2022-11-14 10:21:37 +01:00
enjoy-digital 169ce9e3d0
Merge pull request #450 from Icenowy/stlv7325-enh 
Some enhancements to STLV7325 target code
 2022-11-14 10:05:13 +01:00
Icenowy Zheng e9d7013d70 sitlinv_stlv7325: add jtagbone support 
Add necessary script snippets for enabling jtagbone in the command line.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:28:04 +08:00
Icenowy Zheng c2c59f5e8c sitlinv_stlv7325: allow to set local/remote ip 
Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:58 +08:00
Icenowy Zheng 3d8106f84d stlv7325: fix Ethernet IO voltages 
The IO voltages of Ethernet pins is set to 2.5V instead of 1.5V.

Fix this in the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng 27c3afb8fb sitlinv_stlv7325: allow dynamic Ethernet IP 
Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.

Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00
Icenowy Zheng 4ba5793822 sitlinv_stlv7325: remove unexistent COL/CRS pins 
The COL and CRS pins of the Ethernet PHY is not connected on the board
at all, but assigned dummy positions in the platform definition, which
leads to Vivado warning when building.

Remove these pins from the platform definition.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-11-13 17:27:23 +08:00