fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
f021c1de5f
targets/trellisboard: add '--with-spi-sdcard' build option
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-20 07:14:13 -04:00
69a78c8c66
targets/trellisboard: switch to SoCCore, use add_ethernet() method
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
396b0383c8
platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads
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Add support for SPI-mode SDCard interface. Also, add pull-up and
slew constraints to the standard sdcard interface.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-03-19 18:09:37 -04:00
d0d047dfa4
platforms/ulx3s: add spisdcard pins.
2020-03-19 15:14:05 +01:00
6ab13a0661
de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.
2020-03-19 11:09:48 +01:00
db9d5489ec
Merge pull request #56 from rob-ng15/master
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de10nano add in support for MiSTer secondary sd card
2020-03-19 11:07:40 +01:00
57bcadb5b4
platforms/nexys4ddr: add spisdcard pins.
2020-03-19 11:04:11 +01:00
f3d7f5880f
platforms/kcu105: fix pcie tx0 p/n swap.
2020-03-18 19:09:52 +01:00
bc6ef0bc48
Allow access to secondary sd card via hardware spi bitbanging
2020-03-18 12:13:37 +00:00
a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging
2020-03-18 12:11:57 +00:00
a99d258411
targets/icebreaker: use simplified version closer to the others targets.
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Add description of the board, link to the crowdsupply campaign and to the more complete example.
2020-03-13 09:43:43 +01:00
74a5ffb9ef
targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock.
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The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
2020-03-10 16:58:30 +01:00
e2a66090ee
targets/Ultrascale(+): simplify CRG using USIDELAYCTRL.
2020-03-10 16:55:22 +01:00
cf58550bba
targets/Ultrascale+: use USPDDRPHY.
2020-03-10 16:06:48 +01:00
ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5
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platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:30:12 +01:00
90de99eb46
platforms/mercury_xu5: fix sdram timing issues
2020-03-10 15:03:31 +01:00
75286f8a9b
platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31)
2020-03-10 14:57:39 +01:00
95e1a05bf1
platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF.
2020-03-09 09:29:49 +01:00
3f191c8561
mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4).
2020-03-09 09:28:25 +01:00
f4ae21a7a2
zcu104: fix copyrights.
2020-03-09 09:24:06 +01:00
5031c11d57
mercury_xu5: add missing copyrights.
2020-03-09 09:23:08 +01:00
8c535d15f2
platforms/mercury_xu5: replace ' with ".
2020-03-09 09:21:27 +01:00
dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5
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add Enclustra Mercury XU5 board
2020-03-09 09:11:15 +01:00
2b1b9684de
targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset.
2020-03-07 18:25:26 +01:00
9416ddd84a
targets/icebreaker: simplify arguments and make it closer to others targets.
2020-03-07 18:13:02 +01:00
992f7066fa
targets/icebreaker: simplify leds.
2020-03-07 18:12:59 +01:00
682316214c
targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy.
2020-03-07 18:12:52 +01:00
f777d4b08c
targets/icebreaker: +x
2020-03-05 23:11:35 +01:00
6f517ad1d6
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
2020-03-05 10:57:59 +01:00
d002059e0b
add Enclustra Mercury XU5 board
2020-03-05 10:52:32 +01:00
7776764580
Merge pull request #51 from esden/icebreaker
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Add iCEBreaker FPGA support
2020-03-05 10:35:50 +01:00
745c99ba14
icebreaker: Updated to build on newer litex. Disabled bios building.
2020-03-05 00:12:18 -08:00
3ac9d927a9
targets: icebreaker: Minor style fixes.
2020-03-05 00:12:18 -08:00
738967176c
targets: icebreaker: set the boot address to point to SPI flash
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
093e4913c4
targets: icebreaker: hack to get boot working
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
77b780eb4b
targets: icebreaker: switch to single SPI
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The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
e6dcdc31ed
targets: icebreaker: fix cpu and add spi flash
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
0185095782
targets: icebreaker: fix argument parsing for cpu
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
f0dd31f6c8
target: targets: add crg and begin getting it working
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Signed-off-by: Sean Cross <sean@xobs.io>
2020-03-05 00:12:18 -08:00
ce9b67e2ee
Added icebreaker platform and target.
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Target is heavily based on Fomu.
2020-03-05 00:12:18 -08:00
fd6c555117
Merge pull request #50 from TomKeddie/tomk_20200228_colorlight_connectors
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platforms/colorlight_5a_75b: add J1-J8 connectors
2020-02-28 19:11:30 +01:00
7b4ca20ff4
platforms.colorlight_5a_75b: add J1-J8 connectors
2020-02-28 06:09:44 -08:00
be5ed35871
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
2020-02-28 09:46:54 +01:00
b44885d222
vc707: fix copyrights (Michael Betz is the initial author)
2020-02-28 08:39:52 +01:00
b89af28a05
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
2020-02-27 12:58:52 +01:00
edcc2cf63e
test_targets: add vc707, zcu104, vcu118 and colorlight_5a_75b
2020-02-27 11:17:28 +01:00
aaa10c69eb
platforms/colorlight_5a_75b: add default_clk_name/period
2020-02-27 11:16:49 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
18f65a7f9d
platforms/kc705: cleanup ddram.
2020-02-27 11:06:35 +01:00
Florent Kermarrec
Gabriel Somlo
rob-ng15
Jędrzej Boczar
Piotr Esden-Tempski
Sean Cross
Tom Keddie