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1,388 Commits 9 Branches 14 Tags 11 MiB
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1388 Commits

Author SHA1 Message Date
rob-ng15 a6f80694cb
Add in support for secondary sd card via spi hardware bitbanging 2020-03-18 12:11:57 +00:00
Florent Kermarrec a99d258411 targets/icebreaker: use simplified version closer to the others targets. 
Add description of the board, link to the crowdsupply campaign and to the more complete example.
 2020-03-13 09:43:43 +01:00
Florent Kermarrec 74a5ffb9ef targets/Ultrascale+: use 500MHz IDELAYCTRL reference clock. 
The minimum is 300MHz on Ultrascale+ vs 200MHz on Ultrascale.
 2020-03-10 16:58:30 +01:00
Florent Kermarrec e2a66090ee targets/Ultrascale(+): simplify CRG using USIDELAYCTRL. 2020-03-10 16:55:22 +01:00
Florent Kermarrec cf58550bba targets/Ultrascale+: use USPDDRPHY. 2020-03-10 16:06:48 +01:00
enjoy-digital ce922613a7
Merge pull request #55 from antmicro/jboc/mercury-xu5 
platforms/mercury_xu5: fix sdram timing issues
 2020-03-10 15:30:12 +01:00
Jędrzej Boczar 90de99eb46 platforms/mercury_xu5: fix sdram timing issues 2020-03-10 15:03:31 +01:00
Florent Kermarrec 75286f8a9b platforms/zcu104: add missing INTERNAL_VREF on bank 64 (DQ0-31) 2020-03-10 14:57:39 +01:00
Florent Kermarrec 95e1a05bf1 platforms/Ultrascale: avoid unnecessary {{}} on INTERNAL_VREF. 2020-03-09 09:29:49 +01:00
Florent Kermarrec 3f191c8561 mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4). 2020-03-09 09:28:25 +01:00
Florent Kermarrec f4ae21a7a2 zcu104: fix copyrights. 2020-03-09 09:24:06 +01:00
Florent Kermarrec 5031c11d57 mercury_xu5: add missing copyrights. 2020-03-09 09:23:08 +01:00
Florent Kermarrec 8c535d15f2 platforms/mercury_xu5: replace ' with ". 2020-03-09 09:21:27 +01:00
enjoy-digital dc1371108d
Merge pull request #52 from antmicro/jboc/mercury-xu5 
add Enclustra Mercury XU5 board
 2020-03-09 09:11:15 +01:00
Florent Kermarrec 2b1b9684de targets/icebreaker: simplify CRG, just use a 12MHz sys_clk and por_clk for reset. 2020-03-07 18:25:26 +01:00
Florent Kermarrec 9416ddd84a targets/icebreaker: simplify arguments and make it closer to others targets. 2020-03-07 18:13:02 +01:00
Florent Kermarrec 992f7066fa targets/icebreaker: simplify leds. 2020-03-07 18:12:59 +01:00
Florent Kermarrec 682316214c targets/icebreaker: use specific method to set Yosys/Nextpnr settings. Rename argument to nextpnr-xxyy. 2020-03-07 18:12:52 +01:00
Florent Kermarrec f777d4b08c targets/icebreaker: +x 2020-03-05 23:11:35 +01:00
Florent Kermarrec 6f517ad1d6 targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis. 2020-03-05 10:57:59 +01:00
Jędrzej Boczar d002059e0b add Enclustra Mercury XU5 board 2020-03-05 10:52:32 +01:00
enjoy-digital 7776764580
Merge pull request #51 from esden/icebreaker 
Add iCEBreaker FPGA support
 2020-03-05 10:35:50 +01:00
Piotr Esden-Tempski 745c99ba14 icebreaker: Updated to build on newer litex. Disabled bios building. 2020-03-05 00:12:18 -08:00
Piotr Esden-Tempski 3ac9d927a9 targets: icebreaker: Minor style fixes. 2020-03-05 00:12:18 -08:00
Sean Cross 738967176c targets: icebreaker: set the boot address to point to SPI flash 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross 093e4913c4 targets: icebreaker: hack to get boot working 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross 77b780eb4b targets: icebreaker: switch to single SPI 
The Icebreaker doesn't have the QE/ bit set in config, so default to
using single SPI.

Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross e6dcdc31ed targets: icebreaker: fix cpu and add spi flash 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross 0185095782 targets: icebreaker: fix argument parsing for cpu 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Sean Cross f0dd31f6c8 target: targets: add crg and begin getting it working 
Signed-off-by: Sean Cross <sean@xobs.io>
 2020-03-05 00:12:18 -08:00
Piotr Esden-Tempski ce9b67e2ee Added icebreaker platform and target. 
Target is heavily based on Fomu.
 2020-03-05 00:12:18 -08:00
enjoy-digital fd6c555117
Merge pull request #50 from TomKeddie/tomk_20200228_colorlight_connectors 
platforms/colorlight_5a_75b: add J1-J8 connectors
 2020-02-28 19:11:30 +01:00
Tom Keddie 7b4ca20ff4 platforms.colorlight_5a_75b: add J1-J8 connectors 2020-02-28 06:09:44 -08:00
Florent Kermarrec be5ed35871 targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). 2020-02-28 09:46:54 +01:00
Florent Kermarrec b44885d222 vc707: fix copyrights (Michael Betz is the initial author) 2020-02-28 08:39:52 +01:00
Florent Kermarrec b89af28a05 targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. 2020-02-27 12:58:52 +01:00
Florent Kermarrec edcc2cf63e test_targets: add vc707, zcu104, vcu118 and colorlight_5a_75b 2020-02-27 11:17:28 +01:00
Florent Kermarrec aaa10c69eb platforms/colorlight_5a_75b: add default_clk_name/period 2020-02-27 11:16:49 +01:00
Florent Kermarrec d8de4fbdfb platforms/targets: keep in sync with LiteX 2020-02-27 11:06:53 +01:00
Florent Kermarrec 18f65a7f9d platforms/kc705: cleanup ddram. 2020-02-27 11:06:35 +01:00
Florent Kermarrec d4460c11a5 platforms/kcu105/vcu118: remove PRE_EMPHASIS/EQUALIZATION on dm. 2020-02-27 10:43:41 +01:00
Florent Kermarrec 58f588f69e platforms/zcu104/ddram: add PRE_EMPHASIS/EQUALIZATION settings 2020-02-27 10:43:01 +01:00
Florent Kermarrec d87b8b3c66 zcu104: add separate ddram_32/64 definitions and use ddram_32 for now. 
Ease switching between ddram_32 and ddram_64.
 2020-02-27 10:05:17 +01:00
Florent Kermarrec 8ecfb13f3c zcu104: add copyrights 2020-02-27 09:57:26 +01:00
enjoy-digital 22b0449509
Merge pull request #47 from antmicro/zcu104 
Add support for ZCU104 board
 2020-02-27 09:51:54 +01:00
Piotr Binkowski 608541d5b8 add ZCU104 board 2020-02-26 13:53:21 +01:00
Florent Kermarrec e516ff3452 vcu118/ddram: use similar IO settings than Xilinx's MIG, comment unused pins. 2020-02-26 10:16:51 +01:00
Florent Kermarrec 9d2ca50c5f kcu105/ddram: use similar IO settings than Xilinx's MIG, comment unused pins. 2020-02-26 10:16:35 +01:00
Florent Kermarrec 83d2c71099 platforms/vcu118: add missing Internal Vref configuration on DDR4 C1/C2 banks 2020-02-25 18:32:42 +01:00
Florent Kermarrec 4a84e9b08a targets/colorlight_5a_75b: add instruction to build/load and use bitstream with wishbone-tool 2020-02-25 12:47:08 +01:00