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1263 Commits

Author SHA1 Message Date
Florent Kermarrec 5b4558c9b9 platforms/efinix_trion_t120_bga576: Add Buttons and Serial (other PMOD USB-UART). 2021-10-13 16:32:58 +02:00
Florent Kermarrec a4d178a740 Add Efinix Trio T120 BGA576 Dev-Kit initial support (LedChaser). 2021-10-13 12:29:53 +02:00
Florent Kermarrec 83e64fbd64 targets/qmtech_10cl006: +x. 2021-10-13 12:16:41 +02:00
Florent Kermarrec e29bcd30a6 litex_acorn_baseboard: Add some M2 signals and set devslp to 0. 2021-10-12 11:54:17 +02:00
Florent Kermarrec a365362f5d Rename litex_m2_baseboard to litex_acorn_baseboard and add link to repository. 2021-10-11 18:36:12 +02:00
Florent Kermarrec fe08491e8d litex_m2_baseboard: Add LCD. 2021-10-11 18:30:23 +02:00
enjoy-digital 393252ddc9
Merge pull request #277 from hansfbaier/master 
Add support for QMTech 10CL006 board
 2021-10-11 14:01:06 +02:00
enjoy-digital 79fe4a9199
Merge pull request #275 from alainlou/master 
rz_easyfpga: cleanup and ease of use
 2021-10-11 13:57:06 +02:00
Florent Kermarrec 2b2c7d3d68 trellisboard: Add PMOD GPIO support (for tests with MicroPython). 2021-10-11 11:33:13 +02:00
Florent Kermarrec 9e18d9bc34 gsd_butterstick: Remove ECLKBRIDGECS (not required). 2021-10-07 14:09:22 +02:00
Hans Baier d119b598c5 Add support for QMTech 10CL006 board 2021-10-05 12:06:41 +07:00
alainlou 1b676f929a cleanup and ease of use 
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
 2021-10-03 13:21:45 -04:00
Florent Kermarrec f0a629774a test/test_targets: Add excluded_platforms/targets lists and add quicklogic_quickfeather to it. 2021-10-01 13:53:05 +02:00
Florent Kermarrec e8611794b4 Add initial QuickLogic QuickFeather support (Led Chaser). 
Untested.
 2021-10-01 10:58:26 +02:00
Florent Kermarrec de4ad324cb mnt_rkx7: Revert default sys_clk_freq to 100MHz. 2021-09-30 18:03:22 +02:00
Florent Kermarrec 1858273945 mnt_rkx7: Add SPI SDCard support. 2021-09-30 18:01:54 +02:00
Florent Kermarrec 05f3158311 mnt_rkx7: Increase default sys_clk_freq to 125MHz. 2021-09-30 16:22:18 +02:00
Florent Kermarrec 1217e94218 mnt_rkx7: Switch DDR3 to IS43TR16512B now added to LiteDRAM. 2021-09-30 15:45:40 +02:00
Florent Kermarrec 9bcae49629 mnt_rkx7: Add I2C (For the SiI9022A). 2021-09-30 15:33:53 +02:00
Florent Kermarrec 4f7c18a503 mnt_rkx7: Add Ethernet/Etherbone support. 2021-09-30 15:14:03 +02:00
Florent Kermarrec 84f0d715ff mnt_rkx7: Add SDCard support. 2021-09-30 11:34:23 +02:00
Florent Kermarrec 31b404c42f mng_rkx7: Add SPI Flash support. 2021-09-30 11:29:56 +02:00
Florent Kermarrec df7fe5687e Add initial MNT Reform Kintex-7 module (RKX7) support with Clk, UART and DDR3. 
Compiles but untested on hardware.
 2021-09-30 11:06:39 +02:00
Florent Kermarrec 82653cf66f icebreaker/fomu: Fix SPRAM split. 2021-09-30 09:32:26 +02:00
Florent Kermarrec 5addd7f7d8 icebreaker/fomu: Split PSRAM in half: 64kB SRAM/64kB RAM). 
Allows building bare metal demo and running it directly on these boards.
 2021-09-29 19:33:22 +02:00
enjoy-digital dfa572083a
Merge pull request #273 from ozbenh/wukong-v2 
Wukong board improvements
 2021-09-28 13:22:42 +02:00
Florent Kermarrec 2089c2b708 ci: Install meson (now required by picolibc). 2021-09-27 16:21:43 +02:00
Alessandro Comodi 228245075a boards: added datacenter DDR4 RDIMM tester board 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-27 10:15:55 +02:00
Benjamin Herrenschmidt 4a52996106 Wukong board improvements 
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.

Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.

This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2021-09-24 12:13:56 +10:00
enjoy-digital f18b10d1ed
Merge pull request #249 from Quiddle11/atlys 
Initial Digilent Atlys support
 2021-09-23 10:21:49 +02:00
Florent Kermarrec 921c300b50 digilent_atlys: Simplify/Remove entropy... 
Build tested with ./digilent_atlys.py --with-ethernet --build.
 2021-09-23 10:17:54 +02:00
enjoy-digital 7778f1fc93
Merge pull request #272 from alainlou/master 
rz_easyfpga: adjust SDRAM clk phase, also add 1:2 rate
 2021-09-23 09:01:17 +02:00
alainlou 1333f89ed6 rz_easyfpga: adjust SDRAM clk phase 
- also add 1:2 rate
 2021-09-22 00:26:28 -04:00
Alain Lou 610e82d774
Add initial RZ-EasyFPGA support! (#270) 2021-09-21 09:55:22 +02:00
Florent Kermarrec d5eea94289 sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs). 2021-09-20 11:46:10 +02:00
Florent Kermarrec 5190c9c869 sipeed_tang_nano_4k: Initial Video Out support. 
With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
 2021-09-20 09:32:20 +02:00
Florent Kermarrec 30756ce05e targets: Update to VideoHDMIPHY. 2021-09-20 09:30:32 +02:00
Florent Kermarrec 7161ad18ec sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL. 2021-09-20 08:40:19 +02:00
Florent Kermarrec a5c5ba7652 sipeed_tang_nano_4k: Integrate HyperRam (not yet working). 2021-09-17 16:30:39 +02:00
Florent Kermarrec 376a836583 sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader. 
./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2021-09-17 15:57:55 +02:00
Florent Kermarrec 28571308bc sispeed_tang_nano: Add simple UART loopback test... (Not working...) 2021-09-16 19:34:48 +02:00
Florent Kermarrec 5955a35372 Add initial Sipeed Tang Nano support (Clk/Leds/Buttons). 2021-09-16 19:22:30 +02:00
Florent Kermarrec c0aed8a727 litex_m2_baseboard: Add Video Terminal support. 2021-09-16 18:54:50 +02:00
Florent Kermarrec 32a9256f3b litex_m2_baseboard: Add SDCard support. 2021-09-16 18:17:34 +02:00
Florent Kermarrec 0854a5d234 litex_m2_baseboard: Add Ethernet/Etherbone support. 2021-09-16 18:02:55 +02:00
Florent Kermarrec 8d2f75ca6d litex_m2_baseboard: Add PMODs connectors. 2021-09-16 17:48:53 +02:00
Florent Kermarrec 3ad0eb6992 Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons. 2021-09-16 17:44:50 +02:00
Tim Ansell 67756e53ae
Merge pull request #269 from kammoh/readme_zybo_fpga 
Update README.md
 2021-09-15 07:34:20 -07:00
Kamyar Mohajerani b75af2f21c
Update README.md 
FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
 2021-09-15 10:21:10 -04:00
Florent Kermarrec 078b1ed7b7 CONTRIBUTORS: Update. 2021-09-15 14:59:42 +02:00