e4a15f6064
targets/alinx_axau15: Remove unwanted add_sdcard() call.
2024-04-23 11:40:01 +02:00
110c051779
add Alientek DaVinci Pro FPGA board
2024-04-22 13:46:39 +07:00
aaab2dcfe2
alinx_axau15: Add PCIe speed support (Gen3 or Gen4) and add SDCard parameter.
2024-04-19 14:35:13 +02:00
3dc2fb9c0d
ti60_f225_dev_kit: Remove Ethernet/Etherbone debug that is no longer useful.
2024-04-12 12:21:36 +02:00
fad45b45c1
targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart
2024-04-11 15:12:17 +02:00
24db5783c1
adi_adrv2crr: Fix typo in PMOD pinout
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-04-10 14:06:47 +02:00
62b5b58aec
platforms,targets/xilinx_zc706: added choice between vivado(default) and openFPGALoader, re-enable DDR
2024-04-08 20:38:09 +02:00
3bd14f541e
platforms/xilinx_zc706: added missing i2c node
2024-04-05 10:47:33 +02:00
d2d38794f4
Merge pull request #579 from hansfbaier/qmtech-altera-sdram-attrs
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Better Altera SDRAM IO properties for more speed
2024-04-04 10:56:37 +02:00
cb84141cec
Merge pull request #578 from hansfbaier/qmtech-optional-core-resources
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qmtech core boards: make core resources optional
2024-04-04 10:56:02 +02:00
44ab802ae6
Merge pull request #577 from hansfbaier/qmtech-ddr3-fix
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qmtech_artix7_fgg676/fbg484: fix wrong memory chip type
2024-04-04 10:55:06 +02:00
bce119e0c3
litex_acorn_baseboard_mini: Proper fix to allow simultaneous Ethernet and SATA.
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Tested successfully with ./litex_acorn_baseboard_mini.py --with-etherbone --with-sata --build --load.
-> Able to ping 192.168.1.50
-> Able to initialize SATA:
litex> sata_init
Initialize SATA...
Model: WDC WDS120G1G0A-00SS50
Capacity: 120GB
Successful.
2024-04-04 10:52:56 +02:00
d24e69c112
litex_acorn_baseboard_mini: Try to share QPLL to allow enabling SATA and Ethernet/Etherbone simultaneously.
2024-04-03 12:04:36 +02:00
934002e7e6
targets/alinx_axau15: Avoid USPHBMPCIEPHY workaround.
2024-04-02 12:46:11 +02:00
e4c4391a9c
colorlight_i9plus: Switch to OpenFPGALoader for loading bitstreams.
2024-04-02 08:44:25 +02:00
7d89aa0fe9
qmtech altera boards: sdram io properties for more speed
2024-03-30 20:43:41 +07:00
2392473b89
targets/xilinx_zc706: typo ZCU -> ZC
2024-03-30 11:54:28 +01:00
af1cdc4ed9
qmtech core boards: make core resources optional
2024-03-30 09:59:22 +07:00
a72f2a2e68
targets/xilinx_zc706: typo...
2024-03-29 07:18:19 +01:00
27dce96bf8
targets/xilinx_zc706: SFP/etherbone working: added a note to use it
2024-03-29 07:16:53 +01:00
917ae33351
targets/xilinx_zc706: temporary disabled ddr3
2024-03-29 07:11:06 +01:00
5629f9e97a
qmtech_artix7_fgg676: fix wrong memory chip type
2024-03-29 08:41:19 +07:00
2505aeb9b4
qmtech_wukong: Switch to direct instance of LiteEthPHYGMII since hybrid MII/GMII does not seems to work correctly.
2024-03-28 16:02:55 +01:00
b6b3226192
qmtech_wukong: Add --remote-ip argument.
2024-03-28 15:50:54 +01:00
4ca13943eb
qmtech_wukong: Change --board-version to --revision as on other boards.
2024-03-28 15:30:57 +01:00
4df2ab98e7
qmtech_wukong: Add V3 support and minor cleanups.
2024-03-28 15:23:58 +01:00
9235468ce1
qmtech_wukong: Minor cleanups.
2024-03-28 14:50:03 +01:00
57a9970257
xilinx_zc706: ADD DDR3 support in target and update/fix IOs definition in platform (Untested on hardware).
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- Use/Mimic IO standards from KC705.
- Keep it to single rank for now (but add dual rank IOs in comments).
- Add DCI cascade property.
- Add sys4x and idelay clocking.
- Add LiteDRAM PHY/Core support.
2024-03-27 08:51:30 +01:00
ded90748ee
xilinx_kc705: Minor Cleanup/Update.
2024-03-27 08:48:05 +01:00
d582515af4
Merge pull request #576 from trabucayre/zc706_next
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xilinx_zc706: Add missing peripherals/resources.
2024-03-27 08:26:44 +01:00
e51b9eb392
sipeed_tang_mega_138k_pro: Fix previous commit.
2024-03-26 22:05:20 +01:00
40c7a63e53
Finish tang_mega_138k renaming to tang_mega_138k_pro.
2024-03-26 21:58:02 +01:00
6ec1cfe401
xilinx_zc706: add missing peripherals/resources
2024-03-26 21:57:21 +01:00
d5038dec61
Merge pull request #572 from AlanCui4080/master
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Rename sipeed_tang_mega_138k.py to sipeed_tang_mega_138k_pro.py
2024-03-26 21:55:11 +01:00
8a5b83125b
xilinx_zc706: Add Ethernet/Etherbone support through SFP/K7_1000BaseX (Untested on hardware).
2024-03-26 21:53:45 +01:00
a29532b5d7
xilinx_zc706: Add PCIe Gen2 X4 support (Untested on hardware).
2024-03-26 21:41:41 +01:00
fdd4edbd1a
xilinx_zc706: Review/Minor changes.
2024-03-26 21:35:10 +01:00
6b35c47e8b
xilinx_zc706: new Xilinx/AMD Zynq7000 based board
2024-03-26 20:49:54 +01:00
1655cbf62f
alinx_axau15: Add manual loc constraints on PCIe GTHE4 channels to avoid Vivado to remap them.
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Board now correctly seen with lspci.
2024-03-26 14:12:26 +01:00
8f7ba0ae28
Merge pull request #573 from Xilokar/master
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Fix sqrl_acorn proxy bitstream for cle-101
2024-03-26 12:36:56 +01:00
02ab7ee692
Merge pull request #571 from skrutt/master
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Correct pinout for VGA connector
2024-03-26 12:35:37 +01:00
cc7f092520
alinx_axau15: Fix PCIe support compilation (still needs proper instance name).
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Not yet working on hardware.
2024-03-25 19:11:33 +01:00
191a5bb17a
alinx_axau15: Add RGMII Ethernet/Etherbone support.
2024-03-25 16:08:38 +01:00
9d083eb8bd
sqrl_acorn: the litefury (cle-101 variant is a xc7a100t, so use the right proxy when flashing
2024-03-22 10:01:43 +01:00
11bf6ea703
targets/siglent_sds1104xe.py: added note on how to use crossover with jtagbone
2024-03-20 16:58:38 +01:00
785bf15bba
prog/openocd_xc7z_ft232.cfg: openOCD config file for zynq7000 with digilent hs2 probe (tested with siglent SDS1104XE).
2024-03-20 16:56:44 +01:00
8dea12d48f
platforms/fairwaves_xtrx: Update with developments from XTRX-Julia project and simplify variants/switch to openFPGALoader.
2024-03-19 11:49:48 +01:00
abaa6b9a90
Rename sipeed_tang_mega_138k.py to sipeed_tang_mega_138k_pro.py
2024-03-19 17:21:21 +08:00
f50ee97520
alinx_axau15: Minor adjustments.
2024-03-14 15:13:59 +01:00
e980798437
gsd_orangecrab: Add --without_dfu_rst argument to allow disabling reset to DFU on Button press.
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This is useful in some case where were button input is force through hardware change to force DFU to be in reset at startup.
2024-03-11 17:23:42 +01:00
Florent Kermarrec
Hans Baier
Gwenhael Goavec-Merou
Sylvain Munaut
Xilokar
AlanCui