inc
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
Gwenhael Goavec-Merou
4e06e5ff9c
targets/xilinx_zybo_z7: adding missing variant parameter to the platform
2022-12-14 07:47:09 +01:00
JoyBed
d28894a4b3
Reintroduce original Zybo + HDMI addition ( #461 )
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* Reintroduce original Zybo support
* Reintroduce original zybo, add HDMI + fixes for Z7
2022-12-12 22:05:47 +01:00
Florent Kermarrec
12db52471d
targets/jungle_electronics_fireant: Update SPIFlash (Make it similar to other boards with BIOS in SPIFlash).
2022-12-08 08:37:13 +01:00
enjoy-digital
c05ce32c8a
Merge pull request #458 from trabucayre/arty_s7_tcl_config
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Arty z7 tcl config
2022-12-08 08:31:22 +01:00
Tim Callahan
6e205be83b
Add LedChaser to iCEBreaker-bitsy.
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Signed-off-by: Tim Callahan <tcal@google.com>
2022-12-04 17:58:20 -08:00
Gwenhael Goavec-Merou
a889321535
targets/digilent_arty_z7: adding note to load gateware and bios
2022-12-03 16:54:52 +01:00
Gwenhael Goavec-Merou
e71e3ab3ec
platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration
2022-12-03 16:54:39 +01:00
Gwenhael Goavec-Merou
b030630237
Merge pull request #453 from cklarhorst/zybo
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Zybo: Fix for Zynq7000 and use ps7 as submodule for Soft-CPUs
2022-11-25 21:48:43 +01:00
mkuhn99
53b6bf035a
fixed parser
2022-11-24 16:03:12 +01:00
mkuhn99
926ed21f0b
fixed review remarks; added zynq7000 as a submodule for using the ps as a slave
2022-11-23 17:20:25 +01:00
mkuhn99
c489347a51
fixed zynq7000 integration; introduced option to add the processing-system as slave to the SoC
2022-11-18 11:19:57 +01:00
Icenowy Zheng
892bf3546d
isx_im1283: connect CRG reset to PLL
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This fixes soft reset.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-16 15:12:18 +08:00
Icenowy Zheng
e27d8c958e
isx_im1283: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-15 21:07:10 +08:00
Florent Kermarrec
ae47172d2a
targets/decklink_mini_4k: Update clock constraints.
2022-11-14 10:21:42 +01:00
Icenowy Zheng
e9d7013d70
sitlinv_stlv7325: add jtagbone support
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Add necessary script snippets for enabling jtagbone in the command line.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:28:04 +08:00
Icenowy Zheng
c2c59f5e8c
sitlinv_stlv7325: allow to set local/remote ip
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Port the script snippet from Colorlight i5 for setting the local/remote
IP address to STLV7325.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:58 +08:00
Icenowy Zheng
27c3afb8fb
sitlinv_stlv7325: allow dynamic Ethernet IP
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Currently the sitlinv_stlv7325 target script parses the option that
selects dynamic Ethernet IP; however it's not really passed to LiteETH.
Really pass this option and add an assert that does not allow dynamic
Etherbone IP like other boards.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Icenowy Zheng
1c07fa94ca
sitlinv_stlv7325: fix ident string vendor name
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As we changed the vendor name to proper Sitlinv in the file name, the
ident string is left untouched.
Fix this too.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-11-13 17:27:23 +08:00
Florent Kermarrec
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
Florent Kermarrec
a8c92cd86f
targets/simple: Switch back to old version for now.
2022-11-08 11:55:06 +01:00
Florent Kermarrec
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
Florent Kermarrec
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
Florent Kermarrec
16b9677acd
targets: Switch to soc_core_argdict.
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The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
Florent Kermarrec
f1e24046fd
xilinx_alveo_u250: Fix.
2022-11-06 22:17:28 +01:00
Florent Kermarrec
9a2028a9ba
targets: Remove useless argparse imports.
2022-11-06 22:09:21 +01:00
Florent Kermarrec
30723b1bb0
targets: Update targets that were still using argparse.ArgumentParser.
2022-11-06 22:07:17 +01:00
Florent Kermarrec
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
Gwenhael Goavec-Merou
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
Icenowy Zheng
d7184fb043
stlv7325, a_e115fb: use the proper vendor name Sitlinv
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The boards are in fact from a vendor called 成都赛特凌威科技有限公司,
and their English registered trademark (used on the banner of their
Taobao store) is Sitlinv, which sounds like 赛特凌威.
Use this vendor name instead of where it's bought.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-30 10:51:13 +08:00
enjoy-digital
4dc8f7223c
Merge pull request #443 from trabucayre/arty_z7_bios
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targets/digilent_arty_z7: adding software support
2022-10-28 10:42:35 +02:00
Florent Kermarrec
3e809c3a1e
targets: Fix some LiteXModule imports.
2022-10-28 10:35:57 +02:00
Florent Kermarrec
ab3ed624cc
fpgawars_alhambra2: +x.
2022-10-28 10:31:49 +02:00
Gwenhael Goavec-Merou
5f1b80fac4
targets/digilent_arty_z7: adding software support
2022-10-27 21:47:32 +02:00
Florent Kermarrec
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
Chema
f9d3a39001
chore fix target, args processing
2022-10-26 20:45:53 +02:00
Chema
189ee3de39
fix target
2022-10-26 20:36:18 +02:00
Chema
54af30a4be
fix: arg cpu-variant
2022-10-26 20:23:14 +02:00
Chema
32be05cfb1
chore default CPU variant
2022-10-25 21:14:25 +02:00
Chema
125569b2cb
add FPGAWars Alhambra II
2022-10-25 21:12:02 +02:00
Florent Kermarrec
bd2f1c2553
targets/isx_im1283: Fix CI.
2022-10-22 16:23:50 +02:00
enjoy-digital
8e35f15c22
Merge pull request #437 from trabucayre/fix_redpitaya_mem_region
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targets/redpitaya: fix csr & reset region
2022-10-22 16:00:22 +02:00
enjoy-digital
474dcb5fb3
Merge pull request #436 from Icenowy/isx-im1283
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Add ISX iM1283 board
2022-10-22 15:56:43 +02:00
Florent Kermarrec
5a8d846a86
targets: Remove add_csr calls (no longer required).
2022-10-21 08:42:24 +02:00
Gwenhael Goavec-Merou
4a5d5318d7
targets/redpitaya: fix csr & reset region
2022-10-20 16:35:57 +02:00
Icenowy Zheng
745ebbbfa1
Add ISX iM1283 board
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ISX iM1283 is a "simple eDP signal generator" which utilizes a XC7A100T
FPGA, and come with a header populated with the FPGA's JTAG.
This commit adds initial reverse engineered IOs including the DDR3 DRAM
(which cannot work reliably @ DDR3-800, so the system clock is defaultly
set to 80MHz now), two LEDs and SD slot.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-10-14 22:50:43 +08:00
Gwenhael Goavec-Merou
e44e63f65d
targets/digilent_arty_z7: add flash region
2022-10-13 19:48:41 +02:00
Franck Jullien
3ec18c3583
Add qmtech Cyclone IV Starter Kit
2022-10-09 16:34:44 +02:00
Florent Kermarrec
e6762e228c
targets/mnt_rkx7: Make USB-Host optional and disable by default (for CI).
2022-10-04 09:45:51 +02:00
Florent Kermarrec
d0dd009329
targets/mnt_rkx7: Integrate specific eDP video timings in target (Avoid LiteX patch).
2022-10-04 09:29:59 +02:00