Commit Graph

9663 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 1a845d4553 32-device, 8-bit CSR bus 2011-12-17 15:54:49 +01:00
Sebastien Bourdeauducq bb21f7584a 32-device, 8-bit CSR bus 2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq 1b3edd07ca norflash tb: use get_fragment 2011-12-17 15:22:26 +01:00
Sebastien Bourdeauducq 6f8a6db40a verilog: get the simulator to run the combinatorial process at the beginning 2011-12-17 15:20:22 +01:00
Sebastien Bourdeauducq 0e30d67fa3 Multiply system clock 2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq 85fbe07b94 clkfx module 2011-12-17 15:00:11 +01:00
Sebastien Bourdeauducq ec47394012 verilog: support for float parameters in instances 2011-12-17 14:59:27 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq ee6ca729a2 verilog: user-definable reset and clock 2011-12-16 22:25:05 +01:00
Sebastien Bourdeauducq 738b45dcbd Support the new FHDL syntax 2011-12-16 21:30:22 +01:00
Sebastien Bourdeauducq c7b9dfc203 fhdl: simpler syntax 2011-12-16 21:30:14 +01:00
Sebastien Bourdeauducq 39b7190334 Pay a bit more attention to PEP8 2011-12-16 16:02:55 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq 929cc98070 wishbone2csr: wait for WB deack 2011-12-13 17:38:59 +01:00
Sebastien Bourdeauducq b487e99bcf Initial import 2011-12-13 17:33:12 +01:00
Sebastien Bourdeauducq 22d03b4943 timeline: only trigger in rest state 2011-12-13 15:25:46 +01:00
Sebastien Bourdeauducq 6f7a35e0a3 examples: Wishbone interconnect test bench 2011-12-13 14:10:56 +01:00
Sebastien Bourdeauducq c840848dba verilog: use blocking assignment in combinatorial process 2011-12-13 14:09:12 +01:00
Sebastien Bourdeauducq 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
Sebastien Bourdeauducq 0ea7a9b2e6 wishbone2csr: fix double-write bug 2011-12-13 00:25:46 +01:00
Sebastien Bourdeauducq 923fc52e68 wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
Sebastien Bourdeauducq a72faaecdd fhdl: allow a namespace to be specified for Verilog conversion 2011-12-13 00:24:40 +01:00
Sebastien Bourdeauducq eee6980a36 fhdl: support Constant parameters for Verilog conversion 2011-12-11 20:17:51 +01:00
Sebastien Bourdeauducq dafef5d744 fhdl: fix list references (thanks Lars) 2011-12-11 20:17:29 +01:00
Sebastien Bourdeauducq 16a6029a1b bus: fix CSR interconnect data readback 2011-12-11 20:17:12 +01:00
Sebastien Bourdeauducq dad9120653 bus: 14-bit CSR addresses 2011-12-11 20:16:50 +01:00
Sebastien Bourdeauducq 7582b76406 bank: fix csrgen address decoder 2011-12-11 20:15:30 +01:00
Sebastien Bourdeauducq 05d91c7104 bus: Wishbone to CSR bridge 2011-12-11 15:04:34 +01:00
Sebastien Bourdeauducq af74a89b8a corelogic: timeline module 2011-12-11 01:11:13 +01:00
Sebastien Bourdeauducq 019ef16db4 fhdl: remove broken fragment iadd 2011-12-11 01:10:59 +01:00
Sebastien Bourdeauducq b00581616e convtools: insert reset on variables 2011-12-11 01:10:37 +01:00
Sebastien Bourdeauducq d3127fd5d8 autofragment: remove debug 2011-12-10 20:48:23 +01:00
Sebastien Bourdeauducq 44f44b8a05 fhdl: autofragment 2011-12-10 20:47:21 +01:00
Sebastien Bourdeauducq 4b15a84505 fhdl: fix += for empty fragment 2011-12-10 20:47:06 +01:00
Sebastien Bourdeauducq a49ecc4331 fhdl: pad support in fragments 2011-12-10 20:25:24 +01:00
Sebastien Bourdeauducq 4d1a960308 wishbone: decoder + shared bus interconnect 2011-12-09 13:11:52 +01:00
Sebastien Bourdeauducq fa63cc1ec8 fhdl: replication support 2011-12-09 13:11:34 +01:00
Sebastien Bourdeauducq 5c7131dc86 wishbone: arbiter 2011-12-08 23:21:25 +01:00
Sebastien Bourdeauducq c1041b9a5f simplebus: export GetSigName function 2011-12-08 23:06:04 +01:00
Sebastien Bourdeauducq b2bc5ad4f4 corelogic: multimux module 2011-12-08 23:04:34 +01:00
Sebastien Bourdeauducq b0c5b74c22 verilog: handle default in case statements 2011-12-08 23:04:20 +01:00
Sebastien Bourdeauducq 512655c108 fhdl: improve automatic signal naming 2011-12-08 21:28:20 +01:00
Sebastien Bourdeauducq 5034af3038 Corelogic conversion example 2011-12-08 21:25:05 +01:00
Sebastien Bourdeauducq 62f70a54f0 corelogic: MC divider module 2011-12-08 21:19:40 +01:00
Sebastien Bourdeauducq 84eb964adc fhdl: support negation operator 2011-12-08 21:15:44 +01:00
Sebastien Bourdeauducq bf021efa2b verilog: fix unary operator conversion 2011-12-08 21:15:24 +01:00
Sebastien Bourdeauducq 78f18ad593 corelogic: round-robin module 2011-12-08 21:15:02 +01:00
Sebastien Bourdeauducq 7c99e51b90 Named buses 2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq 5720a51dad wishbone: add missing SEL 2011-12-08 19:09:32 +01:00
Sebastien Bourdeauducq ed05ec5f6a instances: signal override 2011-12-08 18:56:14 +01:00