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9634 Commits

Author SHA1 Message Date
Florent Kermarrec 5257ddaac0 ci: Build/Install GHDL from sources. 2024-05-28 14:33:05 +02:00
Dolu1990 9165886525 snyc 2024-05-28 12:59:27 +02:00
Matthias Breithaupt 025149c6c5 liblitespi: Fix #1967 
Make liblitespi independent from field_access_functions, since they were removed in 46911d5078

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-05-28 11:27:02 +02:00
Dolu1990 2dac84f32c vexii l2 now support self flush. ex : 
--l2-self-flush=40c00000,40DD4C00,1666666
 2024-05-27 17:37:30 +02:00
Fin Maaß ae13f159c4 litex_json2dts_zephyr.py: include cpu 
include cpu, to share the clock-frequency with
zephyr.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-05-27 11:29:58 +02:00
Florent Kermarrec 47bab2fcff CHANGES.md: Update. 2024-05-27 08:41:58 +02:00
enjoy-digital 2235c711e6
Merge pull request #1964 from acceleratedtech/jwise/output-load-trion 
efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion
 2024-05-27 08:40:49 +02:00
enjoy-digital aa9ad61674
Merge pull request #1962 from VOGL-electronic/master 
Add support for the Efinix reconfiguration interface
 2024-05-27 08:36:40 +02:00
Joshua Wise 7ad3f2ce34 efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion 2024-05-24 18:10:24 -04:00
Matthias Breithaupt eed89ba3a3 Add support for the Efinix reconfiguration interface 
This adds low level support for the reconfiguration interface (sometimes also called remote update by Efinix)

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-05-24 08:50:58 +00:00
Dolu1990 4a6efa47c1 Add variants to VexiiRiscv 2024-05-23 16:44:20 +02:00
enjoy-digital 56371c4d9f
Merge pull request #1961 from maass-hamburg/dts_zephyr_include_ctrl 
litex_json2dts_zephyr.py: include ctrl
 2024-05-23 15:52:24 +02:00
Fin Maaß 77683f1659 litex_json2dts_zephyr.py: include ctrl 
include ctrl, needed to implement rebooting
in zephyr.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-05-22 16:16:03 +02:00
Gwenhael Goavec-Merou 0af1ae8c64 soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the PSU's GPIO controler 2024-05-22 15:55:46 +02:00
Gwenhael Goavec-Merou 44d049f3ad litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required when this method is called more than once 2024-05-22 15:53:52 +02:00
Florent Kermarrec 14dbdeb0cb soc/integration/export: Disable fields_access_function by default. 2024-05-21 10:26:18 +02:00
Florent Kermarrec 05030990b2 soc/integration/export: Add LITEX_CSR_ACCESS_FUNCTIONS/LITEX_CSR_FIELDS_ACCESS_FUNCTIONS defines to allow user to disable access functions. 
-DLITEX_CSR_ACCESS_FUNCTIONS=0 to disable CSR access functions.
-DLITEX_CSR_FIELDS_ACCESS_FUNCTIONS=0 to disable CSR access functions.

User can also avoid access function generation on get_csr_header call with:
- with_access_functions=False
- with_fields_access_functions=False
 2024-05-21 10:26:13 +02:00
Florent Kermarrec 5b297f5601 soc/integration_export: Split C header generation by sections. 
- CSR Includes.
- CSR Registers/Fields Definition.
- CSR Registers Access Functions.
- CSR Registers Field Access Functions.
 2024-05-21 10:26:08 +02:00
Florent Kermarrec 4502edd33e soc/integration/export: Prepare split of C header generation in sections. 2024-05-21 10:26:04 +02:00
Dolu1990 06bbbe78e4 vexii/naxii fix floating axi wires 2024-05-20 08:56:38 +02:00
Dolu1990 21e0ec7f98 vexii/naxii fix floating axi wires 2024-05-20 08:55:05 +02:00
Gwenhael Goavec-Merou 10083f4d87
Merge pull request #1958 from nrndda/patch-1 
Simple mistake fix
 2024-05-18 21:33:25 +02:00
Dmitry 2d52c65613
Simple mistake fix 2024-05-18 19:09:13 +00:00
Dolu1990 5eeb999694 update vexii 2024-05-18 16:59:27 +02:00
Dolu1990 8c0f5447ed fix nax/vexii git checkout process, thanks JoyBed 2024-05-18 10:01:29 +02:00
Florent Kermarrec 4b3f147fc8 CHANGES: Update. 2024-05-17 12:58:03 +02:00
enjoy-digital d5f9d57c2b
Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart 
Zynqmp aximaster eth i2c uart
 2024-05-17 12:54:06 +02:00
Gwenhael Goavec-Merou 943c0c263d soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode 2024-05-17 11:02:41 +02:00
Gwenhael Goavec-Merou 49488e5e01 soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode 2024-05-17 11:02:31 +02:00
Gwenhael Goavec-Merou e95edaf9be soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii) 2024-05-17 11:02:16 +02:00
Gwenhael Goavec-Merou 1986b79b9a soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion 2024-05-17 11:02:02 +02:00
Gwenhael Goavec-Merou c5592ca8da soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file 2024-05-17 11:01:46 +02:00
Dolu1990 0720ffb404 Update vexii 2024-05-17 10:00:24 +02:00
enjoy-digital 882463d9db
Merge pull request #1955 from Dolu1990/nax64_irq 
cores/cpu/naxriscv: fix 64 bits IRQ support
 2024-05-17 08:20:46 +02:00
Dolu1990 122e060a5e update vexii 2024-05-16 19:30:15 +02:00
Dolu1990 74b300597b cpu/naxriscv: fix 64 bits IRQ support 2024-05-16 18:59:40 +02:00
Dolu1990 60b0273eda Add baremetal IRQ support 2024-05-16 18:58:16 +02:00
Dolu1990 57f74da8d8 Merge branch 'master' into vexiiriscv 2024-05-16 16:17:21 +02:00
enjoy-digital d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs 
Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
 2024-05-16 10:55:12 +02:00
Florent Kermarrec fbf03ec74c inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it. 
Also cleanup self.mem.get_port call.
 2024-05-16 10:36:44 +02:00
Florent Kermarrec c0d9224f09 integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled. 2024-05-16 09:19:18 +02:00
Dolu1990 d4c1a10817 cores/cpu/naxriscv: Add baremetal IRQ support 2024-05-14 14:57:29 +02:00
Florent Kermarrec e03b097e8e software/libbase/isr.c: Simplify using __riscv_plic__ define. 2024-05-14 14:47:01 +02:00
Florent Kermarrec c79e1ef95f cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag. 2024-05-14 14:43:57 +02:00
Dolu1990 786c929f08 cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE 2024-05-14 14:24:37 +02:00
enjoy-digital 8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework 
Simplify/Cleanup C exports and disable Fields accessors generation by default.
 2024-05-14 12:54:48 +02:00
Florent Kermarrec 8eaa53ae9a test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated). 2024-05-14 12:53:09 +02:00
enjoy-digital c810b89464
Merge pull request #1951 from nuntipat/update-cv32e40p 
Update CV32E40P to be based on the OpenHW Group's repo
 2024-05-14 12:11:50 +02:00
enjoy-digital 9b6e231a1a
Merge pull request #1952 from nuntipat/fix-csr-def-cv32e41p 
Fix CSR register definition for the CV32E41P core
 2024-05-14 12:08:42 +02:00
Florent Kermarrec 46911d5078 soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects). 2024-05-14 11:59:13 +02:00