a763e82d86
soc/builder: add initialize_memory()
...
Allows the target soc to override memory initialization:
rom and/or ram.
2024-04-02 11:37:31 +11:00
5d2676482f
sim/video: Add option to render only on frame vsync
2024-03-29 11:24:16 +10:00
87137c3027
CHANGES.md: Update.
2024-03-28 14:24:12 +01:00
7b0985a6bc
Merge pull request #1909 from davidar/sim-rgba
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sim/video: Change pixel format to RGBA
2024-03-28 14:21:24 +01:00
c73f310179
Merge pull request #1908 from Irvise/neorv32_update
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Update NeoRV32 CPU to v1.9.7
2024-03-28 14:20:59 +01:00
206118c427
Add missing file
2024-03-28 09:16:25 +01:00
c7b2393e34
nax jtag renaming
2024-03-28 09:16:19 +01:00
60920f3c7d
integration/export: Also fix MockCSRRegion base definition.
2024-03-27 17:09:33 +01:00
e74b7f7ebe
integration/export: Fix MockCSRRegion C header export.
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Use full address for export since when used, CSR_BASE is related to the top level SoC and not to the imported external mapping.
2024-03-27 16:49:09 +01:00
1895dd36e2
tools/litex_sim: Add --with-video-colorbars option
2024-03-26 20:23:51 +10:00
6735728340
sim/video: Change pixel format to RGBA
2024-03-26 20:22:58 +10:00
4389742a4f
CHANGES.md: Update.
2024-03-25 19:10:40 +01:00
40ff2da45c
Update NeoRV32 CPU to v1.9.7
2024-03-23 10:18:07 +01:00
9156d7902e
tools/litex_json2dts_linux: increment interrupts value by one for rocket
2024-03-21 20:54:08 +01:00
68108e396d
tools/litex_json2dts_linux: added isa-base,isa-extensions required by kernel > 6.6.0 in replacement to isa
2024-03-21 20:53:19 +01:00
473c52c9d8
Got jtag instruction interface to work
2024-03-21 13:29:40 +01:00
72cb7d3fb7
Fix jtag reset
2024-03-21 13:05:18 +01:00
29aa8f0771
Merge pull request #1906 from jdavidberger/master
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Avoid extra timing delays for NXLRAM path
2024-03-21 09:14:39 +01:00
c640efcec3
Avoid extra timing delays for NXLRAM path
2024-03-20 14:58:08 -06:00
90c1d7b62d
Update the reset topology
2024-03-20 17:56:53 +01:00
edc24b39a4
Got linux + jtag to run in sim
2024-03-20 17:37:51 +01:00
8f04542c15
Revert "build/openocd: Allow config file to be searched from local dirs"
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This reverts commit a7d441488c
2024-03-20 16:44:58 +01:00
46ff7cdee5
Merge pull request #1901 from FlyGoat/zynq7000_openocd
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Zynq7000 litex_server OpenOCD JTAG fixes
2024-03-20 16:41:22 +01:00
d7a862fdd0
wip
2024-03-20 08:09:30 +01:00
9d0fc2c7c2
litex_json2dts_linux: Add support for multiple Ethernet interfaces
2024-03-12 14:42:48 +01:00
c2fd1e9a49
litex_json2dts_linux: Switch to cpu_name instead of cpu_human_name.
2024-03-08 18:53:44 +01:00
49f12ea297
soc/add_cpu: Add CPU_NAME constant.
2024-03-08 18:51:26 +01:00
a7d441488c
build/openocd: Allow config file to be searched from local dirs
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To sort out path for boards using OpenOCD config file shipped with
OpenOCD itself.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-07 19:54:04 +00:00
94e644ba92
Merge pull request #1902 from trabucayre/rocket_update
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Rocket update
2024-03-07 13:38:02 +01:00
68991b6a40
tools/litex_json2dts_linux: added missing rocket's nodes (align to pythondata-cpu-rocket dts)
2024-03-07 11:59:48 +01:00
54f8d90d38
soc/cores/cpu/rocket/core: align config (XCACHE, XTLB) to pythondata-cpu-rocket master
2024-03-07 09:00:32 +01:00
149080fc8b
cpu/naxriscv/core: Minor cleanups and add xlen to human_name.
2024-03-06 16:01:38 +01:00
18720e29cc
build/openocd: Fix tap name for zynq_7000
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zynq_7000 have a special tap name fpr PL defined in openocd
config file.
Just hardcode it here.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-05 21:44:55 +00:00
35dd87499c
build/openocd: Disable polling after init
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OpenOCD's event polling mechanism may interfere with
jtagstream, as we don't expect any command sent by
openocd itself.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2024-03-05 21:34:56 +00:00
f304cba8a6
Merge pull request #1897 from machdyne/master
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support TQFP144 ECP5 package
2024-03-05 21:26:22 +01:00
98c15331be
Merge pull request #1899 from meiniKi/fazyrv_path
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FazyRV: Fix minor typo in path check
2024-03-05 21:24:49 +01:00
1511c8f200
tools/litex_json2dts_linux: don't hardcode phandle for clint's interrupts-extended
2024-03-05 16:10:42 +01:00
12b9c8b2e7
cpu/fazyrv: Fix minor path typo
2024-03-04 21:44:18 +01:00
044760e06c
build/colognechip/colognechip: check if p_r is in PATH before trying to copy dly file
2024-03-02 12:23:10 +01:00
62f275debd
cpu/fazyrv: Expose parameters and fix vdir.
...
On your targets: --cpu-type=fazyrv --help:
CPU options.:
--cpu-chunksize {1,2,4,8}
Size of the chunks, i.e., the data path. (default: 8)
--cpu-conf {MIN,INT,CSR}
Configuration of the processor. (default: MIN)
--cpu-rftype {LOGIC,BRAM,BRAM_BP,BRAM_DP,BRAM_DP_BP}
Implementation of the register file. (default: BRAM_DP_BP)
Then: litex_sim --cpu-type=fazyrv --cpu-chunksize=4 --cpu-rftype=LOGIC
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2024 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 1 2024 10:49:12
BIOS CRC passed (a3cd3faa)
LiteX git sha1: 45835b4b
2024-03-01 10:49:37 +01:00
45835b4b9d
build/colognechip/colognechip: workaround for p_r complaining about a missing dly file (will be fixed by the next CologneChip's toolchain release)
2024-03-01 07:12:11 +01:00
697fb51a32
soc/cores/cpu: Add initial FazyRV support with default variant.
...
It will then be useful to expose the different parameters or create variants.
litex_sim --cpu-type=fazyrv:
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2024 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Mar 1 2024 06:49:55
BIOS CRC passed (1ee1fd74)
LiteX git sha1: 4ca66bbe
2024-03-01 06:52:02 +01:00
eeeffa9ffd
support TQFP144 ECP5 package
2024-02-29 21:30:25 +01:00
4ca66bbee6
interconnect/wishbone/Remapper: Fix src_adr/dst_adr signal size.
2024-02-28 19:11:59 +01:00
722b6da9fb
test/test_wishbone: Improve origin_region_remap_test to test more complex remapping.
2024-02-28 19:11:55 +01:00
3d9db91387
build/colognechip/colognechip: add missing p_r option (-cCP)
2024-02-28 17:17:42 +01:00
83c1adbc94
soc/cores/clock/colognechip: set lock_req to 1 by default and connect locked to USR_PLL_LOCKED_STDY
2024-02-28 17:17:06 +01:00
54d19265a7
build/colognechip/platform: typo bitstream_ext -> _bitstream_ext
2024-02-28 16:12:30 +01:00
8eb5e7b6c1
soc/cores/clock/colognechip: REF_CLK/OUT_CLK: int -> str
2024-02-28 16:11:27 +01:00
cd8ad3714d
soc/interconnect/packet/Dispatcher: Add missing **kwargs.
2024-02-28 13:32:09 +01:00
Andrew Dennison
David A Roberts
Florent Kermarrec
Dolu1990
Fernando Oleo Blanco
Gwenhael Goavec-Merou
jdavidberger
Gwenhael Goavec-Merou
inc
Jiaxun Yang
Meinhard Kissich