c67dfa82cc
Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups
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build: efinix: ifacewriter: some fixes
2024-09-26 17:31:53 +02:00
a825c61385
build: efinix: EfinixTristateImpl: use GPIO Bus
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use the gpio bus for Efinix Tristate implemenation.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
e9a4b178ce
build: efinix: platform.py: add `get_pins_location` and `get_pins_name`
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add `get_pins_location` and `get_pins_name`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
f8dc03810d
build: efinix: use LiteXContext to get platform
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use LiteXContext to get platform.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:41 +02:00
afcc477c4e
efinix: common: replace `is_inclk_inverted`
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replace `is_inclk_inverted` with `in_clk_inv` and `out_clk_inv`.
This way thwe right prop is set in the ifacewriter.py.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:11:39 +02:00
a605e75873
efinix: ifacewriter: remove deprecated GPIO properties
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removes `OE_CLK_PIN_INV` and `OE_CLK_PIN` as they
got deprecated in efinity 2023.1.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
2c3536720c
efinix: ifacewriter: add `in_clk_inv` for GPIO INPUT block
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add `in_clk_inv` for GPIO INPUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
10ab1b76c0
efinix: ifacewriter: fix `out_reg` in GPIO INOUT block
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fix `out_reg` in GPIO INOUT block.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 15:10:03 +02:00
b135f71512
build/efinix/common: Disable SDRInput for now since breaking designs, needs to be investigated.
2024-09-26 12:58:54 +02:00
b5e91473b7
build/efinix/common: Update EfinixSDRInputImpl and minor cleanup.
2024-09-26 11:50:37 +02:00
0e337e2079
Merge pull request #2081 from VOGL-electronic/build_efinix_add_sdr_input
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build: efinix: common.py; add `SDRInput`
2024-09-26 11:43:20 +02:00
a19fbb70c4
Merge pull request #2078 from VOGL-electronic/efinix_add_ipm
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build: efinix: add function to add ip
2024-09-26 11:42:34 +02:00
b11cc8c3eb
Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names
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Efinix iface signal names.
2024-09-26 11:42:02 +02:00
39d292a3c7
build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names.
2024-09-26 10:38:05 +02:00
a3a55fc8fb
build/efinix/common: Directly pass ClockSignal/Signal to blocks and let the build resolve names.
2024-09-26 10:14:42 +02:00
fde9d2e4ad
build/efinix/efinity: Add resolve_iface_signal_names method to automatically resolve ClockSignal/Signal names passed in the blocks.
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Allow the Migen/LiteX build elaboration to resolve signal names and just use it in blocks to avoid name_override workaround.
2024-09-26 10:13:58 +02:00
61f715e6e7
build: efinix: common.py; add `SDRInput`
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add `SDRInput` for efinix
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:17:53 +02:00
c3e87367c3
soc/cores/vexriscv_smp: Add the generation of the default sim config ( https://github.com/litex-hub/linux-on-litex-vexriscv/issues/405 )
2024-09-25 10:38:37 +02:00
b86d76baed
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with empty .fst dumps with short simulations.
2024-09-25 08:56:51 +02:00
8a6264c4f6
build: efinix: add function to add ip
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add function to add efinix IP.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-24 11:59:28 +02:00
c95a6e041c
soc/interconnect/stream: Add Delay module.
2024-09-23 12:23:29 +02:00
b2f63b37cc
CHANGES.md: Update.
2024-09-20 13:00:40 +02:00
427ec10cc4
CONTRIBUTORS: Update.
2024-09-20 12:43:18 +02:00
726d39f40d
LICENSE: Bump year.
2024-09-20 12:39:28 +02:00
baff4c69fe
Merge pull request #2075 from trabucayre/efinix_clkinput_signal
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build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 11:59:06 +02:00
033ec13f08
Merge pull request #2076 from trabucayre/xc7s_jtag
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Spartan7 jtag support
2024-09-19 11:53:55 +02:00
6e9dffdbf5
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported when building with Vivado).
2024-09-19 11:10:51 +02:00
ad2c3fcea7
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation without specifying --cpu-variant.
2024-09-19 09:21:13 +02:00
f1e1f3530e
build/efinix/ifacewriter.py: allows the use of ClockSignal for IN_CLK_PIN (gpio)
2024-09-19 09:14:30 +02:00
aca959b059
build/efinix/common.py: ClkInput: added ClockSignal support
2024-09-19 09:12:36 +02:00
e072156b93
build/xilinx/platform.py: added xc7s to the list of device supporting jtag access
2024-09-19 06:49:44 +02:00
fc68f031a1
soc/cores/jtag.py: added Spartan7 definition for BSCANE2
2024-09-19 06:49:10 +02:00
9bacbe130b
Merge pull request #1974 from motec-research/dts_zephyr_updates
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DTS zephyr updates
2024-09-17 14:58:51 +02:00
a350d2e909
soc/interconnect/stream: Add optional CSR to Multiplexer/Demultiplexer and Crossbar module with mux and demux.
2024-09-13 19:21:26 +02:00
2a19a61e05
build/xilinx/vivado: Fix typo.
2024-09-13 10:39:13 +02:00
99550809b3
Merge pull request #2069 from VOGL-electronic/fix-sim-ethernet
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sim: add HW_PREAMBLE_CRC for ethernet
2024-09-13 08:36:40 +02:00
dc8c1bd9cd
build/xilinx/vivado: Rename opt_directive to vivado_opt_directive for consistency with other directives.
2024-09-12 18:04:25 +02:00
203c9816b2
integration/soc/add_etherbone: Allow 64-bit support now that validated.
2024-09-12 13:39:13 +02:00
2fd8c2cd61
sim: add HW_PREAMBLE_CRC for ethernet
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This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble
is automatically attached by the tap, there is no need to add it from
the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-09-12 10:07:43 +02:00
b41a526e81
Merge pull request #2066 from VOGL-electronic/soc.py_ethernet_mac
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soc.py: add_ethernet: add mac addr constant
2024-09-11 11:54:14 +02:00
11c7b69fd4
Merge pull request #2065 from VOGL-electronic/bios_little_warning_fix
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bios: boot.c: fix warnings
2024-09-11 11:53:52 +02:00
7b3f1509d1
soc.py: add_ethernet: add mac addr constant
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add mac addr constant to add_ethernet,
so it matches the one from add_etherbone.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:21:53 +02:00
3966e3438c
bios: boot.c: fix warnings
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this fixes the warnings, when compiling.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-11 11:15:56 +02:00
dc8b74cc58
Merge pull request #2060 from Dolu1990/efinix-rework
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build/efinix: add a few IO primitives, IO constraints, sdc rework
2024-09-10 18:40:10 +02:00
a80f290d80
soc/cores/clock/efinix.py: fill platform.clks with clkout mapping cd/clk_out_name. litex/build/efinix/ifacewriter.py: generate_lvds: when slow_clk/fast_clk are ClockSignal uses platform.clks to map between domain and signal name
2024-09-10 18:07:34 +02:00
ad09ffc150
soc/cores/clock/efinix.py: register_clkin: uses clkin.name_override as input_signal name when name is not provided and PLL is configured in CORE or INTERNAL mode, create_clkout: added PLL name in clk_name str
2024-09-10 18:03:12 +02:00
109ae17e9e
build/efinix/common.py: replaced i as str by a ClockDomain
2024-09-10 17:56:49 +02:00
458e0057f2
soc/interconnect/wishbone: Add Bypass mode on Cache when cachesize == 0 and similar data_widths.
2024-09-09 18:24:14 +02:00
5cd1a57080
soc/interconnect/wishbone: Cosmetic cleanup on Cache.
2024-09-09 18:16:40 +02:00
e06045c576
Merge pull request #2059 from Dolu1990/vexii-clk-video
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soc/cores/vexiiriscv: update clocks + add video framebuffer support
2024-09-09 14:12:50 +02:00
enjoy-digital
Fin Maaß
Dolu1990
Gwenhael Goavec-Merou
Matthias Breithaupt