3179a27d14
dfii: set data mask
2012-02-23 22:00:51 +01:00
92ac69bae3
dfii: new design
2012-02-23 21:21:07 +01:00
b3ca952a39
s6ddrphy: read path OK in simulation
2012-02-21 17:38:40 +01:00
b4e041ecf1
s6ddrphy: write path OK in simulation
2012-02-20 23:55:20 +01:00
ce51653381
s6ddrphy: generate DQ/DQS/DM OE
2012-02-20 16:13:56 +01:00
cbc3b7fa83
s6ddrphy: DQ/DQS/DM SERDES
2012-02-20 13:45:57 +01:00
4c1e18a9b5
s6ddrphy: clock, address and command
2012-02-19 20:49:56 +01:00
f35cd4a85b
Prepare for new DDR PHY
2012-02-19 18:43:42 +01:00
1e4e092a55
bios: fix function prototypes
2012-02-18 21:06:35 +01:00
026457a98c
Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
2012-02-18 18:12:14 +01:00
5bc840b9c1
DFI injector (untested)
2012-02-17 23:50:10 +01:00
c38de34a21
bios: DDR initialization skeleton
2012-02-17 18:47:04 +01:00
e5927e265f
bios: add flash target using m1nor
2012-02-17 18:16:29 +01:00
48ddbf0c85
Add build Makefile and JTAG load script
2012-02-17 18:09:48 +01:00
c387ce7ce5
Map DDR PHY controls in CSR
2012-02-17 17:34:59 +01:00
5d1dad583b
Connect DDR PHY
...
Doesn't do much for the moment, just to check synthesis/P&R.
2012-02-17 11:04:44 +01:00
cdd58e023b
s6ddrphy: use single-ended DQS
2012-02-17 10:53:58 +01:00
cc5e4ae710
clkfx: remove
2012-02-16 19:30:00 +01:00
204452b0d3
m1crg: make clock feedback pin bidirectional
2012-02-16 18:35:44 +01:00
f36a45edcb
lm32: compatibility with the new instance API
2012-02-16 18:35:22 +01:00
72f9af9d90
Generate all clocks for the DDR PHY
2012-02-16 18:02:37 +01:00
859c9d8849
Use new bus API
2012-02-15 16:55:13 +01:00
1368b666df
s6ddrphy: prepare quilt
2012-02-14 15:52:39 +01:00
b157d84434
README
2012-02-14 15:43:09 +01:00
aef2e4b5e8
Use double quotes for all strings
2012-02-14 13:15:00 +01:00
5165ff7ec3
Include Wishbone to ASMI bridge
2012-02-13 23:12:57 +01:00
0654bf4583
tools: use install and /usr/local (as suggested by David Kuehling)
2012-02-08 15:09:07 +01:00
bfd2bf4ed3
tools: remove bin2hex
2012-02-08 15:08:03 +01:00
755079d7fa
libbase: blocking UART write if IRQs are enabled
2012-02-07 15:12:27 +01:00
73fce59631
software: shell from original BIOS
2012-02-07 15:02:44 +01:00
ef0667d959
software: UART RX demo
2012-02-07 14:12:33 +01:00
506ffab11a
uart: RX support
2012-02-07 14:12:23 +01:00
fb22edc06a
software: enable -Wmissing-prototypes
2012-02-07 13:02:06 +01:00
63f6dece56
software: use the Clang/LLVM compiler
2012-02-07 12:52:34 +01:00
a40b0ea175
software: fix size_t and ptrdiff_t
2012-02-07 12:06:49 +01:00
494c383fa8
software: remove unnecessary IRQ acks
2012-02-07 00:07:25 +01:00
b6b1901bb8
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
4aaf48afb0
software: interrupt driven UART working
2012-02-06 23:53:29 +01:00
58f4f78d2c
sram: fix sub-word write
2012-02-06 23:13:35 +01:00
5cde57cb65
software: use new UART
2012-02-06 17:53:41 +01:00
33f1c456bf
top: connect UART IRQ
2012-02-06 17:45:40 +01:00
5dc875de69
UART: use new bank API and event manager
2012-02-06 17:45:31 +01:00
45529d5941
BIOS: hello world
2012-02-05 20:01:28 +01:00
33da32417a
Update gitignore
2012-02-05 20:01:14 +01:00
9b9a510525
Memory map
2012-02-05 19:54:08 +01:00
17cd8dd479
Add tools
2012-02-05 19:14:24 +01:00
e2317bc83b
flash: remove splash screens
2012-02-05 19:12:33 +01:00
1ad44b6571
software: dependencies the Werner way
2012-02-03 12:25:55 +01:00
1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
b5cb1083ab
sram: fix WE signal
2012-02-03 10:38:17 +01:00
Sebastien Bourdeauducq