aea7308051
mibuild/platforms/minispartan6: rename ftdi_fifo to usb_fifo and fix rd_n/wr_n swap
2015-05-01 15:48:42 +02:00
01e2343978
doc: remove cordic
2015-05-01 14:07:38 +08:00
96bff77c36
add examples tests
2015-05-01 00:50:17 +08:00
1cbc468bda
migen/actorlib/packet: add Packetizer and Depacketizer
2015-04-28 18:44:05 +02:00
0da9311d70
migen/genlib: avoid use of floating point in reverse_bytes
2015-04-27 21:04:18 +02:00
3ce5ff3722
migen/actorlib: add packet.py to manage dataflow packets (Arbiter, Dispatcher, Header definitions, Buffer)
2015-04-27 15:14:38 +02:00
f976b1916a
migen/actorlib/misc: add BufferizeEndpoints
...
BufferizeEndpoints provides an easy way improve timings of chained dataflow modules and avoid polluting code with internals buffers.
2015-04-27 15:12:01 +02:00
e96ba1e46f
migen/genlib/misc: add reverse_bytes
2015-04-27 15:08:10 +02:00
472665b81d
Add a command line option (-use_new_parser yes) to Xilinx XST to force use of the newer parser for older FPGAs.
2015-04-25 23:01:07 +08:00
73a1687562
migen/test: for now desactivate test_generic_syntax (travis-ci's Verilator needs to be upgraded?)
2015-04-24 13:24:52 +02:00
67702f25ab
migen/fhdl/verilog: _printheader/_printcomb, remove default value of arguments which are not used in internal functions. (thanks sb)
2015-04-24 12:54:08 +02:00
bc30fc57e7
migen/fhdl: give explicit names to syntax specialization when asic_syntax is used
2015-04-24 12:14:14 +02:00
61c3efc5f5
migen/test: rename asic_syntax to test_syntax and simplify
2015-04-24 12:00:46 +02:00
b93df693a4
travis: add conda package generation and upload + build doc
2015-04-23 14:15:31 +08:00
7280bdb9d4
Add conda recipe for Migen
2015-04-23 14:15:15 +08:00
2f45d4640b
doc: fix warnings during doc build
2015-04-23 12:34:17 +08:00
e5b170f02d
travis: install verilator
2015-04-22 12:30:03 +08:00
7ec0ecae11
test: add test for asic_syntax
2015-04-22 12:29:07 +08:00
6b5969732a
add Travis CI badge
2015-04-22 12:20:46 +08:00
28dde1e38f
fhdl/verilog: add flag to produce ASIC-friendly output
2015-04-21 09:52:14 +08:00
b8bbaaef3a
Fixing shadowing of global index function.
...
Fixes the following warnings;
```
cc -Wall -O2 -fPIC -Wall -Wshadow -g -O2 -fstack-protector --param=ssp-buffer-size=4 -Wformat -Wformat-security -I/usr/include/iverilog -c -o ipc.o ipc.c
ipc.c: In function ‘ipc_receive’:
ipc.c:98:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
ipc.c:113:17: warning: declaration of ‘index’ shadows a global declaration [-Wshadow]
```
Fixes https://github.com/m-labs/migen/issues/14
2015-04-21 00:26:07 +08:00
f57ee296a9
mibuild/altera: cleanup
2015-04-20 17:17:34 +08:00
65eeb33329
Revert "add I/O standard definitions to mibuild/altera"
...
This reverts commit a889b41060
2015-04-20 16:22:32 +08:00
a889b41060
add I/O standard definitions to mibuild/altera
2015-04-20 10:08:47 +02:00
1b050d98ea
add differential in/out support to mibuild/altera
2015-04-20 10:08:26 +02:00
fd966d70ba
some PEP8 cosmetic
2015-04-20 10:03:08 +02:00
15625236c1
platforms/kc705: add PCIe pins
2015-04-17 00:51:16 +02:00
083d371af4
mibuild: add support for libraries, move .replace("\\", "/") to generic_platform.py and execute it only on Windows machines.
...
We need to support libraries when Migen is used as a wrapper on large VHDL designs using libraries.
2015-04-17 00:11:31 +02:00
ae503bc7b9
travis: disable email notification
2015-04-14 23:45:33 +08:00
9c8c20341f
travis: add IRC notification
2015-04-14 23:30:52 +08:00
9e7dc175a4
Using a newer version of iverilog.
2015-04-14 23:17:13 +08:00
c3c5ffb303
Makefile now uses iverilog-vpi
...
From `man iverilog-vpi`;
> iverilog-vpi is a tool to simplify the compilation of VPI modules for use
> with Icarus Verilog. It takes on the command line a list of C or C++ source
> files, and generates as output a linked VPI module.
Fixes https://github.com/m-labs/migen/issues/11
2015-04-14 23:17:13 +08:00
34207982bc
Adding .egg-info to the .gitignore
2015-04-14 23:17:13 +08:00
903711404e
Adding simple travis-ci build.
...
Fixes https://github.com/m-labs/migen/issues/10
2015-04-14 23:17:13 +08:00
9ca3be0f6c
README: add link to online docs
2015-04-14 23:08:21 +08:00
e2af9ac9a6
Expanding the install instructions a little.
...
This is based on the discussion at https://github.com/m-labs/misoc/issues/6
2015-04-14 23:03:45 +08:00
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
482486706c
mibuild/lattice: adapt diamond to last Migen changes
2015-04-13 21:40:58 +02:00
d83e170872
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 21:33:44 +02:00
89bb90fe2a
global: pep8 (E265)
2015-04-13 21:22:46 +02:00
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
728c15213f
global: pep8 (E222)
2015-04-13 20:55:21 +02:00
69764f2e22
global: pep8 (E401)
2015-04-13 20:54:19 +02:00
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
a2c17cdcef
Merge branch 'master' of https://github.com/m-labs/migen
2015-04-13 09:37:03 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
Florent Kermarrec
Sebastien Bourdeauducq
Alain Péteut
William D. Jones
Yann Sionneau
Guy Hutchison
Tim 'mithro' Ansell