Florent Kermarrec
2c3c6bdf9b
Updating documents from LiteX BuildEnv Wiki
2019-04-28 11:41:33 +02:00
Kurt Kiefer
bf27869ad9
fix vexriscv build
2019-04-28 11:10:20 +02:00
enjoy-digital
2d5bae3def
Merge pull request #175 from mithro/cpu-docs
...
Standardizing `cpu_variants` and adding lots of documentation
2019-04-27 21:24:06 +02:00
Tim 'mithro' Ansell
5cbc5bc199
Adding testing of cpu variants.
2019-04-26 18:57:49 -05:00
Tim 'mithro' Ansell
71a837315a
Work with no `cpu_variant` provided.
2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell
65650919a7
Updating documents from LiteX BuildEnv Wiki
2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell
a43de8195f
Updating documents from LiteX BuildEnv Wiki
2019-04-26 17:44:36 -05:00
Tim 'mithro' Ansell
39c579baa2
Standardize the `cpu_variant` strings.
...
Current valid `cpu_variant` values;
* minimal (alias: min)
* lite (alias: light, zephyr, nuttx)
* standard (alias: std) - Default
* full (alias: everything)
* linux
Fully documented in the [docs/Soft-CPU.md](docs/Soft-CPU.md) file
mirrored from the
[LiteX-BuildEnv Wiki](https://github.com/timvideos/litex-buildenv/wiki ).
Also support "extensions" which are added to the `cpu_variant` with a
`+`. Currently only the `debug` extension is supported. In future hope
to add `mmu` and `hmul` extensions.
2019-04-26 17:44:30 -05:00
Florent Kermarrec
3a2e283613
.gitmodules: use our VexRiscv-verilog
2019-04-27 00:00:55 +02:00
Tim 'mithro' Ansell
e42de8fe52
docs: Adding script to pull useful docs from LiteX BuildEnv's wiki.
2019-04-26 14:28:20 -05:00
Florent Kermarrec
78c09125be
soc/integration/soc_core: fix get_mem_data when not file is not multiple of 4 bytes
2019-04-25 23:43:10 +02:00
Florent Kermarrec
0175f86cb2
soc/integration/soc_core: fix get_mem_data for json files
2019-04-25 18:36:47 +02:00
Florent Kermarrec
4443b5075b
soc/integration/soc_core: add integrated_sram_init
2019-04-25 17:30:03 +02:00
Florent Kermarrec
f27084c6c0
soc/integration/cpu_interface: fix banner in get_mem_header
2019-04-24 22:44:37 +02:00
enjoy-digital
5ec99d94ae
Merge pull request #173 from gsomlo/gls-git-revision
...
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 22:42:36 +02:00
Gabriel L. Somlo
d21cba2f17
build: handle exceptional case when litex/migen not deployed as git repo
2019-04-24 12:50:47 -04:00
Florent Kermarrec
27fbb814ab
tools/remote/csr_builder: allow comments in csv file and cleanup
2019-04-24 12:25:49 +02:00
Florent Kermarrec
e8f3c49127
software/libnet/microudp: rearrange send_packet, add comments and remove txlen padding
2019-04-24 11:32:40 +02:00
Florent Kermarrec
44e0cdda9a
software/libnet/microudp: speed-up ARP by changing timeout/tries
...
First ARP request does not seem to be transmitted (the link is probably not
fully established). Reduce the timeout between tries and increase number of
tries.
2019-04-24 09:55:41 +02:00
Florent Kermarrec
3ee78a5b70
build/tools: fix typo
2019-04-23 18:10:51 +02:00
Florent Kermarrec
f0fe9f3cdf
setup.py: add short names for tools
2019-04-23 17:46:20 +02:00
Florent Kermarrec
9ded2eb20b
tools/litex_term: change TERM prompt to LXTERM
2019-04-23 17:46:02 +02:00
Florent Kermarrec
475deb51ac
build: add migen and litex git revision to generated file
2019-04-23 17:40:24 +02:00
Florent Kermarrec
8b5cf29542
build/tools: git_revision is not doing what we want, return "--------" for now
2019-04-23 17:15:43 +02:00
Florent Kermarrec
228f286747
litex_setup: revert default install behaviour but add --user support
2019-04-23 14:53:00 +02:00
enjoy-digital
9fbbf928ed
Merge pull request #171 from keesj/develop_as_user
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Install development packages in the user directory
2019-04-23 14:41:37 +02:00
Florent Kermarrec
0f60ec35e2
tools/litex_server: fix comms import
2019-04-23 14:25:27 +02:00
Florent Kermarrec
68f12495cf
soc/integration: also add sha-1/date to generated software files
2019-04-23 13:17:54 +02:00
Florent Kermarrec
425741226c
build: add sha-1/date to generated verilog, change git_version to git_revision
2019-04-23 12:59:25 +02:00
Kees Jongenburger
24bdb6487d
Install development packages in the user directory
...
When in development mode install the packages in the user directory using the
--user flag from pip. This allows to install and run without the need for root
access.
2019-04-23 12:23:09 +02:00
Florent Kermarrec
f7c0b118ce
test/test_targets: cover all platforms
2019-04-23 11:38:18 +02:00
Florent Kermarrec
818dfae1e8
boards/platforms/ulx3s: fix default clock
2019-04-23 11:37:29 +02:00
Florent Kermarrec
17b6164cd9
boards/platforms/sp605: apply same simplifications than on others platforms
2019-04-23 11:21:55 +02:00
Michael Betz
24bf02934e
boards/platforms: add SP605
2019-04-23 11:15:42 +02:00
Florent Kermarrec
10cf0fdea3
cores/cpu/vexriscv: fix wrong revert
2019-04-23 11:13:29 +02:00
Florent Kermarrec
d2ad14417a
targets/ac701: cleanup and make it similar to others targets.
...
Still supports EthernetSoC with RGMII and 1000BaseX.
2019-04-23 11:10:35 +02:00
Florent Kermarrec
a24bf72fc7
targets/xilinx: remove keep attribute on clock going to idelayctrl
...
Causes P&R issues with Vivado.
2019-04-23 10:51:36 +02:00
Florent Kermarrec
ea8dbff86e
boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms
2019-04-23 10:50:19 +02:00
Florent Kermarrec
0122982e09
boards/platforms/kc705: provide only one default programmer as others platforms
2019-04-23 10:00:52 +02:00
Vamsi K Vytla
89a590263f
boards: Xilinx ac701 dev board support
2019-04-23 09:48:16 +02:00
Michael Betz
88b882c7e0
build/xilinx/ise.py: write .v file for post synthesis sim
2019-04-23 09:22:48 +02:00
Florent Kermarrec
7396ebbb38
build/xilinx/programmer: cleanup XC3SProg position parameter
2019-04-23 09:20:59 +02:00
Michael Betz
f579cbc603
build/xilinx/programmer: add position parameter to XC3SProg
2019-04-23 09:16:42 +02:00
Vamsi K Vytla
fb4f881857
.gitignore: ignore tilde files
2019-04-23 09:10:11 +02:00
Florent Kermarrec
535d86727a
targets/minispartan6: use S6PLL in CRG
2019-04-23 06:44:29 +02:00
Florent Kermarrec
40342404f2
cores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 06:43:48 +02:00
Florent Kermarrec
0d282f38f9
cores/clock: use common XilinxClocking class for all Xilinx clocking modules
2019-04-23 06:35:39 +02:00
Michael Betz
83699ea0a5
cores/clock: add initial Spartan6 PLL/DCM support
2019-04-23 06:23:00 +02:00
Florent Kermarrec
eff141da2d
build: add git version (sha-1) used to create the scripts
2019-04-23 06:03:12 +02:00
Florent Kermarrec
cc141a64b9
build: scripts are generated by LiteX
2019-04-23 05:38:33 +02:00