a889b41060
add I/O standard definitions to mibuild/altera
2015-04-20 10:08:47 +02:00
1b050d98ea
add differential in/out support to mibuild/altera
2015-04-20 10:08:26 +02:00
fd966d70ba
some PEP8 cosmetic
2015-04-20 10:03:08 +02:00
15625236c1
platforms/kc705: add PCIe pins
2015-04-17 00:51:16 +02:00
083d371af4
mibuild: add support for libraries, move .replace("\\", "/") to generic_platform.py and execute it only on Windows machines.
...
We need to support libraries when Migen is used as a wrapper on large VHDL designs using libraries.
2015-04-17 00:11:31 +02:00
ae503bc7b9
travis: disable email notification
2015-04-14 23:45:33 +08:00
9c8c20341f
travis: add IRC notification
2015-04-14 23:30:52 +08:00
9e7dc175a4
Using a newer version of iverilog.
2015-04-14 23:17:13 +08:00
c3c5ffb303
Makefile now uses iverilog-vpi
...
From `man iverilog-vpi`;
> iverilog-vpi is a tool to simplify the compilation of VPI modules for use
> with Icarus Verilog. It takes on the command line a list of C or C++ source
> files, and generates as output a linked VPI module.
Fixes https://github.com/m-labs/migen/issues/11
2015-04-14 23:17:13 +08:00
34207982bc
Adding .egg-info to the .gitignore
2015-04-14 23:17:13 +08:00
903711404e
Adding simple travis-ci build.
...
Fixes https://github.com/m-labs/migen/issues/10
2015-04-14 23:17:13 +08:00
9ca3be0f6c
README: add link to online docs
2015-04-14 23:08:21 +08:00
e2af9ac9a6
Expanding the install instructions a little.
...
This is based on the discussion at https://github.com/m-labs/misoc/issues/6
2015-04-14 23:03:45 +08:00
3f15699964
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
2015-04-13 21:47:55 +02:00
482486706c
mibuild/lattice: adapt diamond to last Migen changes
2015-04-13 21:40:58 +02:00
d83e170872
global: more pep8
...
we will have to continue the work... volunteers are welcome :)
2015-04-13 21:33:44 +02:00
89bb90fe2a
global: pep8 (E265)
2015-04-13 21:22:46 +02:00
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
5f225c0475
global: pep8 (E225)
2015-04-13 21:11:13 +02:00
728c15213f
global: pep8 (E222)
2015-04-13 20:55:21 +02:00
69764f2e22
global: pep8 (E401)
2015-04-13 20:54:19 +02:00
37ef9b6f3a
global: pep8 (E231)
2015-04-13 20:50:03 +02:00
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
a2c17cdcef
Merge branch 'master' of https://github.com/m-labs/migen
2015-04-13 09:37:03 +02:00
c6904f9d63
sim: fix to support ConvOutput
2015-04-12 14:06:57 +08:00
ff23960657
fhdl/verilog: avoid reg initialization in printheader when reset is not an int.
...
We should be able to reset a signal with the value of another one. Without this change it's not possible to do so since synthesis tools do not support initializing a signal from another one.
2015-04-10 17:18:07 +02:00
181aeb4791
Add example of hamming generator and checker instances
...
--089e01294e809a874205133faa19
Content-Type: text/plain; charset=UTF-8
<div dir="ltr"><br></div>
2015-04-10 16:15:55 +08:00
5d07072783
strace_tailor: make more generic, cleanup
2015-04-10 11:07:16 +08:00
a69741b24e
forgot other cordic files
2015-04-09 12:00:20 +08:00
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
8ce683964a
mibuild/tools/write_to_file: use context manager
2015-04-08 19:41:54 +08:00
90c5512b25
genlib: remove cordic (will live in pdq2)
2015-04-08 11:35:53 +08:00
25e4d2a2db
decorators: remove deprecated semantics
2015-04-05 18:47:45 +08:00
8798ee8d73
decorators: fix stacklevel, export in std
2015-04-05 18:47:45 +08:00
f26ad97624
decorators: fix ControlInserter
2015-04-05 14:44:03 +08:00
db76defa2a
fhdl/visit: remove TransformModule
2015-04-04 20:12:22 +08:00
e702fb7727
decorators: fix class/instance logic
2015-04-04 19:16:58 +08:00
4091af69fd
fhdl/decorators: make the transform logic more idiomatic
...
* the transformers work on classes and instances.
you can now do just do:
@ResetInserter()
@ClockDomainRenamer({"sys": "new"})
class Foo(Module):
pass
or:
a = ResetInserter()(FooModule())
* the old usage semantics still work
* the old DecorateModule is deprecated,
ModuleDecorator has been refactored into ModuleTransformer
(because it not only decorates things)
2015-04-04 19:16:50 +08:00
aac953dd90
vivado: support phys_opt
2015-04-04 19:00:22 +08:00
9506f69390
vivado: add support for pre_synthesis_commands
2015-04-04 19:00:01 +08:00
4522956f11
vivado: make _build_files() a method and rename
2015-04-04 18:59:50 +08:00
1d1189506a
mibuild: support multiple specifications of include file and sources
2015-04-04 18:58:02 +08:00
357c807eb1
Merge branch 'master' of github.com:m-labs/migen
2015-04-02 20:23:12 +08:00
ce429841d5
kc705: fix typo in platform file (LPC definition)
2015-04-02 20:21:20 +08:00
ce0ff1e341
remove use of _r prefix on CSRs
2015-04-02 12:15:56 +02:00
d67f24ddc7
migen/bank/description: remove support of _r prefix in CSRs
2015-04-02 12:13:22 +02:00
e5ddd1263c
remove redundant xilinx_strace_tailor.sh
2015-03-30 18:58:34 +02:00
b469571afe
move xilinx_strace_tailor to tools
2015-03-30 19:42:11 +08:00
c169f0b189
Revert "migen: create VerilogConvert and EDIFConvert classes and return it with convert functions"
...
This reverts commit f03aa76292
2015-03-30 19:41:16 +08:00
Alain Péteut
Florent Kermarrec
Sebastien Bourdeauducq
Tim 'mithro' Ansell
Guy Hutchison
Robert Jordens
Yann Sionneau