dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
f658802ff8
replace use of __dict__ with dir()/xdir()
2013-11-02 16:03:47 +01:00
7e20320b9d
pytholite/io: len -> flen
2013-07-27 15:38:48 +02:00
04ec60541c
pythloite/ExprCompiler: attempt compile-time evaluation first
2013-07-27 15:38:29 +02:00
b68c00d36f
pytholite: fix kwargs handling
2013-07-03 17:20:05 +02:00
0aa58f5dcf
pytholite: support generator arguments
2013-07-03 16:35:07 +02:00
b0d467d744
pytholite: use eval instead of literal_eval
2013-06-28 19:03:55 +02:00
d0caa738bd
FSM: new API
2013-06-25 22:17:39 +02:00
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
72ef4b9683
ioo+pytholite: use new Module API
2013-04-10 23:42:46 +02:00
746acdacd1
ioo: move to genlib
2013-04-10 22:28:53 +02:00
692794a21f
flow: use Module and new Record APIs
2013-04-10 19:12:42 +02:00
2b8dc52c13
Use common definition for FinalizeError
2013-03-09 19:03:13 +01:00
f9acee4e68
corelogic -> genlib
2013-02-22 23:19:37 +01:00
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
47f5fc70e4
pytholite: fix bug with constant assignment to register
2012-12-19 16:21:57 +01:00
9c65402fda
pytholite: prune unused registers
2012-12-19 16:03:05 +01:00
3fae6c8f03
Do not use super()
2012-12-18 14:54:33 +01:00
a67f483f0f
Token: support idle_wait
2012-12-14 19:16:22 +01:00
6f99241585
Move Token to migen.flow.transactions
2012-12-14 15:55:38 +01:00
adb1565d7a
pytholite: fix bit width of selection signal
2012-11-30 17:07:32 +01:00
cfb23c442f
pytholite: support signed registers
2012-11-30 17:07:12 +01:00
50ed73c937
New specification for width and signedness
2012-11-29 21:22:38 +01:00
6eebfce44a
Refactor Case
2012-11-29 01:11:15 +01:00
070652cc39
pytholite/reg: use source id in dictionary
2012-11-29 00:09:35 +01:00
fee22a4631
Remove Constant
2012-11-28 23:18:43 +01:00
74721b206f
pytholite: fix import of _Slice
2012-11-23 21:20:18 +01:00
95122bb778
pytholite/io: support memory
2012-11-23 20:36:09 +01:00
f3efd74dfd
uio: support memories
2012-11-23 16:23:24 +01:00
0b7dd7bdce
pytholite/io: fix Wishbone writes + support sel attribute
2012-11-23 13:40:46 +01:00
4c216d8f11
pytholite/io: support Wishbone reads
2012-11-23 13:09:55 +01:00
0b24a2ff36
pytholite/io: support Wishbone writes
2012-11-23 12:41:50 +01:00
f098c5c695
pytholite/compiler: pass keyword arguments to gen_io
2012-11-23 12:40:57 +01:00
e92af9de59
pytholite/transel: use python3-compatible comparison methods
2012-11-17 23:16:07 +01:00
7add4c6f3c
uio: unified I/O object
2012-11-17 19:54:50 +01:00
eb156af20c
pytholite/io: support token pull
2012-11-16 23:48:41 +01:00
dd9a102a78
pytholite/io: support token push
2012-11-16 19:24:45 +01:00
bf5ce8dc20
pytholite: move expression and register handling to separate modules
2012-11-11 23:48:23 +01:00
f59fd69e34
pytholite/compiler: recognize composite I/O pattern
2012-11-11 18:03:16 +01:00
0b5652bb79
pytholite/compiler: visit_assign_special
2012-11-11 15:52:06 +01:00
687d18a150
pytholite: move FSM management to separate module
2012-11-11 14:30:25 +01:00
409a5570e4
pytholite/compiler: refactor visit_block
2012-11-11 14:17:52 +01:00
fb63698ef4
pytholite/compiler: clean up visit_statement
2012-11-10 23:30:14 +01:00
6ebd1e4503
pytholite: forward 'yield call' statements to io module
2012-11-10 22:59:14 +01:00
48acb1bcfd
pytholite: introduce io module
2012-11-10 21:51:19 +01:00
6776f06a42
pytholite/compiler: support bitslice
2012-11-10 18:04:05 +01:00
37f113c3ea
pytholite/compiler: support range(constants) in for loops
2012-11-10 15:26:13 +01:00
370bab1190
pytholite/compiler: cleanup print statements
2012-11-10 15:10:57 +01:00
39c7dc7d63
pytholite/compiler: support for loops (iterating on lists only)
2012-11-10 15:02:55 +01:00
Florent Kermarrec
Sebastien Bourdeauducq