Andrew Dennison
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08189663ba
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soc/add_spi_flash: fix bios 1x mode support
require both phy and flash support to enable QUAD/QPI capability.
Many flash devices support 4x read but may be on a 1x phy
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2024-02-01 14:37:22 +11:00 |
|
Andrew Dennison
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4dae3a9f4d
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build/openfpgaloader: report command line on error
Helps explain failures
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2024-02-01 14:37:16 +11:00 |
Florent Kermarrec
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f73fbee309
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cores/spi/spi_master: Improve documentation, especially on Raw/Aligned mode and CS control.
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2024-01-30 10:57:09 +01:00 |
|
Florent Kermarrec
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a3904ac26d
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CHANGES.md: Update.
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2024-01-30 09:51:05 +01:00 |
|
Florent Kermarrec
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488247e4f7
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build/efinix/programmer: Define EFXDBG_HOME now required by latest Efinity versions.
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2024-01-30 09:44:52 +01:00 |
Gwenhael Goavec-Merou
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245bed7195
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soc/cores/clock/efinix: fix input clock code for trion when the input clock comes from another PLL
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2024-01-25 17:39:12 +01:00 |
|
Gwenhael Goavec-Merou
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d32095540a
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soc/integration/soc: add_ethernet/add_ip_constants: cast str to int (avoid double quote in soc.h
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2024-01-24 16:06:44 +01:00 |
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Florent Kermarrec
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f543b18d02
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soc/add_ethernet: Refactor local/remote_ip configuration and add basic checks for IP address length + validity.
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2024-01-24 15:28:18 +01:00 |
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enjoy-digital
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115e87ff4f
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Merge pull request #1877 from trabucayre/ethernet_local_remote_ip
soc/integration/soc: add_etherbone: allowing to specify local/remote IP
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2024-01-24 15:15:31 +01:00 |
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Gwenhael Goavec-Merou
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bcde71b051
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soc/integration/soc: add_etherbone: allowing to specify local/remote IP
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2024-01-24 15:13:42 +01:00 |
|
enjoy-digital
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1be3f0297d
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Merge pull request #1876 from trabucayre/vexriscv_configurable_clint_csr_addr
soc/cores/cpu/vexriscv_smp/core: allowing configure CSR/CLINT base address by overriding default value or using args
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2024-01-23 16:27:16 +01:00 |
|
Florent Kermarrec
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c31ec79981
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CHANGES.md: Update.
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2024-01-23 16:02:11 +01:00 |
|
Gwenhael Goavec-Merou
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bb62f7aa63
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soc/cores/cpu/vexriscv_smp/core: allowing configure CSR/CLINT/PLIC base address by overriding default value or using args
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2024-01-22 18:36:51 +01:00 |
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enjoy-digital
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4c07d72af3
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Merge pull request #1874 from trabucayre/naxriscv_arch
soc/cores/cpu/naxriscv fix arch definition and small adjust
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2024-01-19 10:22:43 +01:00 |
Gwenhael Goavec-Merou
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854541d5c7
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soc/cores/cpu/naxriscv/core: adding argument to enable rvc extension
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2024-01-19 07:37:55 +01:00 |
|
Gwenhael Goavec-Merou
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f00d49211b
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soc/cores/cpu/naxriscv/core: force go back previous directory after git clone
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2024-01-18 15:21:37 +01:00 |
|
Gwenhael Goavec-Merou
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4222a585c9
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soc/cores/cpu/naxriscv/core: fix arch definition
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2024-01-18 15:04:09 +01:00 |
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Florent Kermarrec
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b19d992f23
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inteconnect/ahb: Add specific case for 32-bit data width, fix CSR accesses with gowin_ae350.
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2024-01-15 11:40:25 +01:00 |
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Florent Kermarrec
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6b79644108
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cores/cpu/gowin_emcu: Switch to LiteX's UART.
A UART does not cost that much ressources and this avoid specific code/allow simplifying support.
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2024-01-11 13:53:15 +01:00 |
|
Florent Kermarrec
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8aa5958fb7
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cores/cpu: Add intitial gowin_ae350 support.
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2024-01-11 13:11:56 +01:00 |
|
Florent Kermarrec
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e689aab18a
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interconnect/ahb/AHB2Wishbone: Add proper Wishbone sel decoder/support.
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2024-01-11 10:17:22 +01:00 |
|
Florent Kermarrec
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80dfb5ca34
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interconnect/ahb/AHB2Wishbone: Simplify and add proper Address/Data-Phases.
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2024-01-10 12:10:15 +01:00 |
|
Gwenhael Goavec-Merou
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a2c2d70841
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build/gowin/gowin: adding list of additional cst commands (to place resources)
Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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2024-01-10 10:30:41 +01:00 |
|
Gwenhael Goavec-Merou
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31d3325219
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build/gowin/platform: adding mock add_false_path_constraint method
Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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2024-01-10 10:30:36 +01:00 |
|
Gwenhael Goavec-Merou
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91fbc79ac2
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build/gowin/common: adding missing TX/Q1 ODDR signals
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2024-01-08 07:28:56 +01:00 |
|
Florent Kermarrec
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718c26d8fc
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cpu/gowin_emcu: Add interfaces directly to instances and simplify/cleanup to remove some warnings.
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2024-01-04 19:33:43 +01:00 |
|
Florent Kermarrec
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c61d2de13b
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CHANGES.md: Update.
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2024-01-04 15:37:58 +01:00 |
|
Florent Kermarrec
|
cf165d3c2c
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README/Bios: Bump year.
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2024-01-04 15:33:01 +01:00 |
|
Florent Kermarrec
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739a8db8c3
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cpu/gowin_emcu: Specify AHB data_width/address_width.
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2024-01-04 15:30:47 +01:00 |
|
Florent Kermarrec
|
7009299132
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interconnect/ahb: Simplify AHBInterface and add data_width/address_width parameters.
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2024-01-04 15:30:26 +01:00 |
|
Florent Kermarrec
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02f0a96c84
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interconnect/ahb: Add AHB prefix to TransferType/Interface (similar to AXI).
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2024-01-04 15:21:32 +01:00 |
|
Florent Kermarrec
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55e2a1cec6
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cpu/gowin_emcu: Switch pbus to byte addresssing.
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2024-01-04 13:13:21 +01:00 |
|
Florent Kermarrec
|
5bbcda4d5c
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interconnect/ahb/AHB2Wishbone: Fix size check that is too restrictive, can be <= log2_int(ahb.data_width//8).
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2024-01-04 13:12:29 +01:00 |
|
Florent Kermarrec
|
6a6837062a
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cpu/gowin_emcu: Remove interrupt signal since not yet functional/used.
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2024-01-04 10:40:47 +01:00 |
|
Florent Kermarrec
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386854cbd3
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cpu/gowin_emcu: Use crt0.c from cortex_m3.
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2024-01-04 10:38:45 +01:00 |
|
Florent Kermarrec
|
de6fbf1271
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cpu/gowin_emcu: Directly connect AHB interfaces, using for loops make things unclear/difficult to follow.
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2024-01-04 10:33:50 +01:00 |
|
Florent Kermarrec
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b0cde1acdd
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cpu/gowin_emcu: Switch SRAM to 4 SRAMS of 8-bit each.
|
2024-01-04 10:12:36 +01:00 |
|
Florent Kermarrec
|
01520cd638
|
cpu/gowin_emcu: Simplify SRAM.
|
2024-01-04 09:59:17 +01:00 |
|
Florent Kermarrec
|
6d3c955d59
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cpu/gowin_emcu: Increase similarities with cortex_m3 (since gowin_emcu is a Cortex M3).
|
2024-01-04 09:09:18 +01:00 |
|
Florent Kermarrec
|
85ef3bd8a7
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cpu/gowin_emcu: Add missing reset signals.
|
2024-01-03 19:41:03 +01:00 |
|
Florent Kermarrec
|
3f9de470f6
|
cpu/gowin_emcu: Add gcc_flags method and set UART_POLLING in it.
|
2024-01-03 19:15:46 +01:00 |
|
Florent Kermarrec
|
456dda050c
|
cpu/gowin_emcu: Cleanup/Simplify.
|
2024-01-03 19:11:05 +01:00 |
|
Florent Kermarrec
|
3909b1d611
|
build/openfpgaloader: Add kwargs support to flash method and some comments.
|
2024-01-02 13:50:02 +01:00 |
gsomlo
|
acf07a21c9
|
soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865)
Fixes: 002aad7a4
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
|
2024-01-01 13:32:40 -05:00 |
|
enjoy-digital
|
56f61986f0
|
Merge pull request #1862 from dau-dev/tkp/classifiers
Fix classifiers to satisfy format checks
|
2023-12-31 19:17:43 +01:00 |
Tim Paine
|
68cfb6eea0
|
Fix classifiers to satisfy format checks
|
2023-12-28 15:49:31 -05:00 |
|
Florent Kermarrec
|
67cfcadf79
|
setup.py/CHANGES.md: Prepare 2023.12 release.
|
2023-12-25 15:36:10 +01:00 |
|
Gwenhael Goavec-Merou
|
7062e3379f
|
build/efinix/ifacewriter: bypass clks out frequency check for Trion when a feedback clock is used
|
2023-12-20 20:33:15 +01:00 |
|
Gwenhael Goavec-Merou
|
54c58ef8b9
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build/efinix/ifacewriter: reorder FEEDBACK for Trion devices.
|
2023-12-20 20:29:23 +01:00 |
|
Gwenhael Goavec-Merou
|
7d5de90a24
|
soc/cores/clock/efinix: remove 2 output clocks limit, reset o_div_max when a nex vco_max_freq is found
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2023-12-20 20:28:51 +01:00 |