e9ef11620f
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)
2015-05-02 16:22:45 +02:00
1761bfba8a
litescope/frontend/wishbone: add support for packetized mode
2015-05-02 16:22:43 +02:00
ff51bde7f0
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
2015-05-02 16:22:40 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
63b8797978
liteeth: move mac to core
2015-05-02 16:22:35 +02:00
a4617014f4
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)
2015-05-02 16:22:33 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
1832f27220
targets/pipistrello: add flash sizes
2015-05-02 09:59:24 +08:00
5e649a6577
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
2015-05-01 20:45:04 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
a8b8af220a
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
2015-05-01 20:44:59 +02:00
cd3a51ada6
litescope: fix missing source ack on LiteScopeWishboneBridge
2015-05-01 20:44:57 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
23126415d3
litescope: use full name in io.py
2015-05-01 17:49:31 +02:00
23ba1ccb52
targets/minispartan6: add USBSoC (working, should also be usable on pipistrello)
2015-05-01 16:22:45 +02:00
da0fe2ecfb
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.
...
small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
2015-05-01 16:22:26 +02:00
603b4cdc8c
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)
...
- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma
2015-05-01 16:11:15 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
a6f290ac16
liteusb: add ft2232h_sync_tb
2015-04-28 19:05:34 +02:00
28c50112a4
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests
2015-04-28 19:01:03 +02:00
30eed19283
liteusb: continue refactoring and add core_tb (should be almost OK)
2015-04-28 18:58:38 +02:00
7fc96da51c
misoclib/com/uart: remove liteeth dependency (copy/paste error)
2015-04-28 18:53:46 +02:00
d253adee61
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend
2015-04-28 18:51:40 +02:00
453279a7c8
litesata: cleanup link
2015-04-27 15:33:01 +02:00
0c08055014
Merge branch 'master' of https://github.com/m-labs/misoc
2015-04-27 15:28:08 +02:00
dc8d844579
liteusb: begin refactoring and simplification (wip)
2015-04-27 15:22:49 +02:00
91c77d464c
liteeth: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:06:37 +02:00
20dd6d3047
litepcie: use new Migen modules from actorlib (avoid duplications between cores)
2015-04-27 15:05:40 +02:00
1ef81c4d24
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations
2015-04-27 14:51:03 +02:00
ded3f22574
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)
2015-04-27 14:48:14 +02:00
fe867ccf33
litesata: remove icarus_workaround.patch (obsolete)
2015-04-27 14:44:54 +02:00
1d9771f574
spiflash: use SoC defines, add write_to_flash function
2015-04-27 13:42:32 +08:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
07b7c2a13f
liteeth/phy/gmii: add default value for pads_register
2015-04-26 14:54:54 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
130fd19dec
liteeth/core/ip: simplify ip rx checksum control
2015-04-24 11:31:10 +02:00
5b48e7bb52
liteeth: finish with_preamble_crc vs with_hw_preamble_crc renaming
2015-04-24 11:30:35 +02:00
2d56d32009
liteeth/mac/core: simplify and fix padding
2015-04-24 09:36:33 +02:00
ff2d1d9383
litescope: fix read in reg.py
2015-04-20 08:16:31 +02:00
4c0d9f5f36
litescope: remove repeat mode on drivers (not useful) and cleanup
2015-04-18 15:37:38 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
341f635a85
litescope: add PCIe driver (mmap/Sysfs) and use it on litepcie example design
2015-04-18 13:58:20 +02:00
602eaf69c7
litepcie: fix asciiart in make.py
2015-04-17 14:10:32 +02:00
8a822b9deb
litepcie: add litepcie_phy_wrappers to extcores
2015-04-17 13:52:21 +02:00
b4b37fb10e
litepcie: add linux driver + utilities (sysfs + dma)
2015-04-17 13:48:34 +02:00
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
93de581931
soc: add shadow_address parameter
...
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
2015-04-17 13:42:29 +02:00
9666629c4f
soc/cpuif: add with_access_functions parameter
...
When don't necessary need access functions in our csr.h (for example with an X86 CPU)
2015-04-17 13:26:38 +02:00
958f149992
litesata/test: fix PYTHONPATH
2015-04-16 19:49:46 +08:00
68c465ba4c
CONTRIBUTING: minor fixes
2015-04-14 23:01:06 +08:00
Florent Kermarrec
Zach Smith
Sebastien Bourdeauducq