6ec7a24731
software/liblitedram: Fixup overflow in BIST speed math
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With decent burst length, fast RAM and fast clock rate,
the intermediate result can easily overflow 32 bits.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-04-26 23:33:08 +02:00
3959ca39d4
Merge pull request #1282 from cklarhorst/master
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software/bios: Fix build error for targets with sdcard but without main_ram_base
2022-04-25 19:26:47 +02:00
63cda6c7b9
soc/add_ethernet: soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.
2022-04-25 18:44:52 +02:00
bdbb6c0b3f
soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.
2022-04-25 17:49:57 +02:00
6ca890ebc0
software/bios: Fix build error for targets with sdcard but without main_ram_base
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sdcardboot_from_bin assumes that the MAIN_RAM_BASE is set which is not always
the case. This commit deactivates the sdcardboot_from_bin support for targets
without main-ram. In those cases, the boot_from_json method can still be used.
2022-04-25 16:49:59 +02:00
edd98c23cb
interconnect/packet/PacketFIFO: +1 on param_depth to allow dequeuing current while equeuing next.
2022-04-25 15:48:05 +02:00
625261c693
cores/video: Fix depth checks that have to be done in Python, not in logic.
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Fixes https://github.com/enjoy-digital/litex/issues/1198 .
2022-04-22 19:36:46 +02:00
1a713225ea
cpu/cortex_m1/m3: Add gcc_flags property and only keep UART_POLLING mode for now.
2022-04-22 18:44:49 +02:00
38fbe8f4ca
cores/cpu: Add category property (hardcore or softcore) and improve CPU listing.
2022-04-22 18:00:44 +02:00
b607de473d
cpu/cortex_m3: Review/Cleanup (Apply similar changes than for Cortex-M1).
2022-04-22 17:03:02 +02:00
2508b16f38
cpu/cortex_m1: Minor cosmetic changes.
2022-04-22 17:02:05 +02:00
1211cb6ab5
cpu: Add initial Cortex-M3 support.
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can be test with targets from LiteX-Boards and Cortex-M3 sources in execution path:
python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m3 --sy-clk-freq=50e6 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Apr 22 2022 16:23:30
BIOS CRC passed (b390faf0)
LiteX git sha1: 99a03426
2022-04-22 16:41:51 +02:00
99a034268d
cpu/naxriscv: Remove Wishbone import/comments (Now fully AXI/AXI-Lite).
2022-04-22 16:16:45 +02:00
31cfe137d1
cpu/cortex_m1/core: Review/Cleanup.
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- Increase similarities with other CPUs.
- Classify instance signals.
- Use Open instead of Signal on open ports.
- Switch pbus to AXILite instead of Wishbone.
- Directly connect AXI ports.
- Rename connect_jtag to add_jtag.
2022-04-22 16:15:39 +02:00
51eb310b0e
cpu: Add initial Cortex-M1 support.
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Can be tested with targets from LiteX-Boards and Cortex-M1 sources in execution path:
python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m1 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Apr 22 2022 15:04:52
BIOS CRC passed (5773c241)
LiteX git sha1: 6b3a5412
2022-04-22 15:22:23 +02:00
016e1abcff
software/libcompiler_rt: Fix compilation for ARM/Cortex-M1.
2022-04-22 15:16:55 +02:00
e2bf77b0e3
integration/soc: Fix comment typo.
2022-04-22 15:12:49 +02:00
6b3a541241
xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints.
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Use get_nets on internal nets, get_ports on IOs.
2022-04-21 18:15:05 +02:00
08e9cfcd86
soc/usb_acm: Move clone of ValentyUSB to LiteX instead of doing it in each LiteX-Boards target.
2022-04-21 15:43:00 +02:00
ca6378a207
cpu/NaxRiscv: Improve place and route timings robustness
2022-04-20 15:13:09 +02:00
ff6e7bd6ad
cores/uart/Stream2Wishbone: Add asserts on data_width/address_width.
2022-04-20 11:01:21 +02:00
5e451d68f7
Merge pull request #1277 from trabucayre/uart_fix_Stream2Wishbone_v2
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Uart fix stream2 wishbone v2
2022-04-20 10:56:38 +02:00
4e5d1848cc
integration/soc/cpu: Improve cpu-type/cpu-variant listing.
2022-04-20 10:37:03 +02:00
3dbe349dd9
liblitesata/sata_init: Add SATA Read check (Seems to be required with some disks).
2022-04-15 18:01:26 +02:00
a988712974
soc/cores/uart:Stream2Wishbone: remove no more needed data_width/address_width equality test
2022-04-15 17:43:50 +02:00
3cb34e7951
soc/cores/uart:Stream2Wishbone: supress data/address egality assert
2022-04-15 17:41:34 +02:00
557ebcedfb
liblitesata/sata_init: Always reinitialize core on call (Even when already ready).
2022-04-15 13:53:18 +02:00
ceb25445d2
wishbone/sram/burst: First review/Minor cleanups.
2022-04-15 09:03:12 +02:00
9c4778b2c1
Merge pull request #1267 from antmicro/wb-sram-inc-burst
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soc/interconnect/wishbone: Add incrementing address burst mode to SRAM
2022-04-15 08:47:42 +02:00
8b2fc201cf
soc/cores/uart: Add assert data_width == address_width to prevent building broken logic and pass data_width/address_width to Wishbone.
2022-04-15 08:39:45 +02:00
fac39c8210
Merge pull request #1275 from fjullien/efinix_ifacewriter_add_gpio_options
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Efinix ifacewriter add gpio options
2022-04-15 08:19:57 +02:00
08cd4803f3
Merge pull request #1274 from fjullien/fix_efinix_pll
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Fix efinix pll
2022-04-15 08:19:18 +02:00
e86c06c9ff
efinix:clock: improve logging informations
2022-04-14 10:48:51 +02:00
25b4eb7b0b
efinix: dont print info in get_pll_resource
2022-04-14 10:48:51 +02:00
5f9d943d36
efinix: get_free_pll_resource needs to call get_pll_resource
2022-04-14 10:48:51 +02:00
66e49249cc
efinix:ifacewriter: add out_clk_inv and in_clk_inv to gpio block
2022-04-14 10:42:55 +02:00
78c35365e8
efinix:ifacewriter: add in_reg and out_reg to gpio block
2022-04-14 10:42:48 +02:00
63356b8187
cpu/naxriscv: Minor cleanups.
2022-04-14 10:12:45 +02:00
0a738002e0
openocd/jtag: Add JTAG-UART/JTABBone support to Zynq7000/ZynqMPSoC and define all Xilinx IRs for USERX.
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Thanks @smunaut for the initial investigation/implementation. The changes have been minimized to:
- Adding an optional delay in TDI: On Zynq devices, TDI is delayed by 1 TCK to bypass the PS tap.
- Avoiding OpenOCD's -endstate DRPAUSE on Xilinx that does not seem required.
2022-04-14 09:51:03 +02:00
be43ef6424
cpu/NaxRiscv: Now support reset from the jtag
2022-04-12 19:38:36 +02:00
8c1bc139ab
soc/interconnect/wishbone: Cleanup in burst cycles support logic
2022-04-12 15:32:29 +02:00
ad46a57403
test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle
2022-04-12 14:06:22 +02:00
cdd216f692
test/test_wishbone: Add basic test for SRAM with burst cycles support
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Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
2022-04-12 14:06:22 +02:00
c00ca99ea9
soc/interconnect/wishbone: Add burst params to Interface test functions
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This commit also replaces hardcoded CTI signal values with constants.
2022-04-12 14:06:22 +02:00
83ea56aeee
soc/interconnect/wishbone: Move burst cycles support option to SoCBusHandler/SoC classes
2022-04-12 14:06:22 +02:00
ca78f799e1
soc/integration/soc_core: Add SRAM/ROM burst cycles support switch
2022-04-12 14:06:22 +02:00
54f897f446
soc/interconnect/wishbone: Make burst cycles support in SRAM optional
2022-04-12 14:06:22 +02:00
8ef51a00ee
soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM
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This commit adds support for incrementing burst cycles in SRAM peripheral.
By default it's enabled, but can be disabled by passing `burst=False`
to the class while initializing, if it won't be useful for created design
(e.g. no Wishbone bus masters with burst support).
2022-04-12 14:06:22 +02:00
7416943f9c
cores/usb_fifo: Re-implement FT245PHYSynchronous, passing simple tests on FT601/LimeSDRMini-V2.0.
2022-04-11 19:23:58 +02:00
7187ac22e4
interconnect/axi: Add AXSIZE dict definition.
2022-04-11 19:20:22 +02:00
Sylvain Munaut
enjoy-digital
Christian Klarhorst
Ilia Sergachev
Dolu1990
Gwenhael Goavec-Merou
Franck Jullien
Rafal Kolucki