0bac463780
sim/icarus: add vpi directory to module search path
...
This allows running the iverilog simulations from the migen top directory
without having to install the .vpi anywhere.
2014-09-07 16:49:12 +08:00
3d84a7a9de
cordic: round() constants if not power of two bitwidth, cleanup, simplify some logic
2014-09-07 16:49:12 +08:00
11f58862db
test_cordic: stop spewing out numbers
2014-09-07 16:49:12 +08:00
4def6ec391
flow/network: replace NetworkX MultiDiGraph with simple implementation
2014-09-07 16:48:46 +08:00
683643266f
cordic: vivado is bad at inferring compact adder/subtractor logic
2014-09-04 15:25:34 +08:00
bd232f3f61
fhdl.structure: do not permit clock domain names that start with numbers
2014-08-18 11:01:56 +08:00
ac2e961618
fhdl.structure: remove unused imports
2014-08-18 11:01:56 +08:00
6036fffef2
Signal.__getitem__: raise TypeError and IndexError when appropriate
2014-08-18 11:01:56 +08:00
b3d69913cd
Signal.like: pass kwargs
2014-08-18 11:01:56 +08:00
60706e4b70
bus/dfi: add CKE and RESET_N
2014-08-09 10:56:08 +08:00
b124a98d92
genlib: add reset synchronizer
2014-08-06 19:38:37 +08:00
8baa957539
genlib/fifo: use synchronous memory read instead of additional register
...
The latter causes problems with InsertReset
2014-08-02 08:52:49 +08:00
44c6e524ba
migen.fhdl.structure: add Signal.like(other)
...
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
2014-07-24 23:52:59 -06:00
9fcea6e64a
migen/sim/generic: use kwargs to pass parameters to icarus.Runner
2014-07-24 10:17:54 -06:00
10d639d313
flow.plumbing: spelling
2014-07-19 14:29:51 -06:00
9266e10cae
flow.plumbing: make argument order consistent
2014-07-19 14:29:50 -06:00
ff1d105c7e
genlib/SyncFIFO: remove flush signal (use InsertReset instead)
2014-07-17 19:15:45 -06:00
ea0f4706f5
fsm: set reset_state as default state
2014-06-22 15:21:22 +02:00
4c426b36f3
fifo: add support for depth=2
2014-06-15 23:58:46 +02:00
70a2ee4368
migen/bank/description: add reset parameter to CSRStatus
2014-06-15 23:54:38 +02:00
9c1d95f6a4
wishbone2lasmi: fix wordbits computation
2014-05-01 13:32:18 +02:00
29ed3918cc
fhdl: forbid zero-length signals
2014-04-18 15:01:50 +02:00
86f852a5f1
wishbone2lasmi: support lasmim data_width < wishbone data_width
2014-04-18 15:00:53 +02:00
a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
135a4fea25
fhdl/verilog: fix representation of negative integers
...
Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
d6cb981c7a
migen/test/test_signed: add a (currently failing) signed comparison testcase
2013-12-10 23:33:53 +01:00
487df5b174
migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)
2013-12-10 23:32:12 +01:00
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
86ba9c8bbc
migen.fhdl.size: verify fslice for negative values
2013-12-03 21:39:37 +01:00
c71eb5778f
migen.fhdl.structure: have Cat() flat_iteration-ize its arguments
2013-12-03 21:36:33 +01:00
1bf133755e
migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things
2013-12-03 21:36:33 +01:00
fe67210d77
migen.fhdl.size: add fiter(), fslice(), and freversed()
...
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
2013-12-03 21:36:33 +01:00
ae6b78faeb
genlib/divider: fix diff computation
2013-12-02 17:56:03 +01:00
dd24fdd356
genlib/sort: add bitonic, combinatorial sorter
...
complete with with api documentation and unittests
2013-12-02 12:56:36 +01:00
Robert Jordens
Sebastien Bourdeauducq
Florent Kermarrec
Sebastien Bourdeauducq