Sebastien Bourdeauducq
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ecfe1646ec
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fhdl/verilog: implicit get_fragment
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2013-03-12 16:16:06 +01:00 |
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Sebastien Bourdeauducq
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c06a821452
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generic_platform: implicit get_fragment
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2013-03-12 16:14:13 +01:00 |
|
Sebastien Bourdeauducq
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4ada2ead05
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fhdl/specials/Memory: automatic name#
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2013-03-12 15:58:39 +01:00 |
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Sebastien Bourdeauducq
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04df076fba
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bank: automatic register naming
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2013-03-12 15:45:24 +01:00 |
|
Sebastien Bourdeauducq
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7e2581bf17
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fhdl/tracer: recognize CALL_FUNCTION_VAR opcode
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2013-03-12 13:48:09 +01:00 |
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Sebastien Bourdeauducq
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12158ceadf
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fhdl/tracer: recognize LOAD_DEREF opcode
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2013-03-12 10:31:56 +01:00 |
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Sebastien Bourdeauducq
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3c75121783
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fhdl/tracer: remove leading underscores from names
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2013-03-11 22:21:58 +01:00 |
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Sebastien Bourdeauducq
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c4d9734e53
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README: update
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2013-03-11 20:29:47 +01:00 |
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Sebastien Bourdeauducq
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80970b203c
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bus/asmibus: use implicit finalization
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2013-03-11 17:11:59 +01:00 |
|
Sebastien Bourdeauducq
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b042757187
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Fix Register name conflict between Pytholite and Bank
|
2013-03-10 19:47:21 +01:00 |
|
Sebastien Bourdeauducq
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f93695f60e
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bank/eventmanager: use module and autoreg
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2013-03-10 19:29:05 +01:00 |
|
Sebastien Bourdeauducq
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174e8cb8d6
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bus/asmibus: use fhdl.module API
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2013-03-10 19:28:22 +01:00 |
|
Sebastien Bourdeauducq
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17e0dfe120
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fhdl/module: replace autofragment
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2013-03-10 19:27:55 +01:00 |
|
Sebastien Bourdeauducq
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cddbc1157d
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bank/description/AutoReg: check that get_memories and get_registers are callable
|
2013-03-10 18:11:29 +01:00 |
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Sebastien Bourdeauducq
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68fe4c269c
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bank/csrgen: BankArray
|
2013-03-10 00:45:16 +01:00 |
|
Sebastien Bourdeauducq
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f1474420df
|
bank/description: AutoReg
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2013-03-10 00:43:16 +01:00 |
|
Sebastien Bourdeauducq
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d0676e2dd1
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migen/fhdl/autofragment: factorize
|
2013-03-09 23:23:24 +01:00 |
|
Sebastien Bourdeauducq
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d0d2df3c4b
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fhdl/autofragment: remove legacy functions
|
2013-03-09 23:05:45 +01:00 |
|
Sebastien Bourdeauducq
|
72fb6fd6bd
|
fhdl/tools/flat_iteration: generalize
|
2013-03-09 23:03:15 +01:00 |
|
Sebastien Bourdeauducq
|
f53acb92e7
|
fhdl/autofragment: fix submodules
|
2013-03-09 21:15:38 +01:00 |
|
Sebastien Bourdeauducq
|
6da8eb906f
|
fhdl/autofragment: empty build_fragment by default
|
2013-03-09 19:10:47 +01:00 |
|
Sebastien Bourdeauducq
|
2b8dc52c13
|
Use common definition for FinalizeError
|
2013-03-09 19:03:13 +01:00 |
|
Sebastien Bourdeauducq
|
b75fb7f97c
|
csr/SRAM: support for writes with memory widths larger than bus words
|
2013-03-09 00:50:57 +01:00 |
|
Sebastien Bourdeauducq
|
6fa30053bf
|
fhdl/verilog: tristate outputs are always wire
|
2013-03-06 11:30:52 +01:00 |
|
Sebastien Bourdeauducq
|
4d4d6c1f88
|
platforms/m1: add video mixer extension board
|
2013-03-05 23:03:01 +01:00 |
|
Sebastien Bourdeauducq
|
9b4ca987e0
|
bus/csr: support memories with larger word width than the bus (read only)
|
2013-03-03 19:27:13 +01:00 |
|
Sebastien Bourdeauducq
|
bb5ee8d3bd
|
fhdl/autofragment: bugfixes + add auto_attr
|
2013-03-03 17:53:06 +01:00 |
|
Sebastien Bourdeauducq
|
cc8118d35c
|
fhdl/autofragment: FModule
|
2013-03-02 23:30:54 +01:00 |
|
Sebastien Bourdeauducq
|
d2491828a4
|
csr/SRAM: prefix page register with memory name
|
2013-03-01 12:06:12 +01:00 |
|
Sebastien Bourdeauducq
|
6a412f796e
|
xilinx_ise: add lock cycle to bitgen
|
2013-03-01 11:29:40 +01:00 |
|
Sebastien Bourdeauducq
|
c10622f5e2
|
fhdl/verilog: insert reset before listing signals
|
2013-02-27 18:10:04 +01:00 |
|
Sebastien Bourdeauducq
|
d2cbc70190
|
bank/description: memprefix
|
2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
|
a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
|
425de02f42
|
uio/ioo: fix specials
|
2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
|
2b902fdcbd
|
xilinx_ise: import Instance
|
2013-02-24 15:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
d60ab1d215
|
Use new 'specials' API
|
2013-02-24 12:21:01 +01:00 |
|
Sebastien Bourdeauducq
|
56ae0f0714
|
xilinx_ise: disable SRL extraction on synchronizers
|
2013-02-23 19:43:12 +01:00 |
|
Sebastien Bourdeauducq
|
ef833422c7
|
generic_platform/get_verilog: pass additional args to verilog.convert
|
2013-02-23 19:42:29 +01:00 |
|
Sebastien Bourdeauducq
|
0321513726
|
corelogic -> genlib
|
2013-02-23 19:37:27 +01:00 |
|
Sebastien Bourdeauducq
|
c2d54f481f
|
examples/psync: cleanup
|
2013-02-23 19:14:31 +01:00 |
|
Sebastien Bourdeauducq
|
6abac5907b
|
examples/basic/psync: demonstrate the new features
|
2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
|
a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
587f50cf90
|
doc: new 'specials' API
|
2013-02-22 18:12:42 +01:00 |
|
Sebastien Bourdeauducq
|
49cfba50fa
|
New 'specials' API
|
2013-02-22 17:56:35 +01:00 |
|
Sebastien Bourdeauducq
|
44ae20d3c4
|
generic_platform: prefix subsignals
|
2013-02-20 18:27:04 +01:00 |