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7216 Commits

Author SHA1 Message Date
Florent Kermarrec ae1d43b965 software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
enjoy-digital c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement 
Replace libbase with picolibc
 2021-09-27 16:05:24 +02:00
Florent Kermarrec 944732aa19 soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone. 2021-09-27 15:46:19 +02:00
Florent Kermarrec ce0551b44a cpu/rocket/core: Remove ResetInserter on adapters. 
Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
 2021-09-27 09:05:46 +02:00
enjoy-digital c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp 
Rocket SMP support
 2021-09-23 10:56:06 +02:00
Gabriel Somlo 07e47d9357 cpu/rocket: add quad-core (smp) variants 
- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
 2021-09-22 16:59:04 -04:00
Gabriel Somlo 901b19828c cpu/rocket: include core count as per-variant parameter 
Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
 2021-09-22 16:58:11 -04:00
Gabriel Somlo e6aaa40d2d cpu/rocket: bios support for SMP 2021-09-22 13:51:18 -04:00
Gabriel Somlo 2bc8124114 cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic) 2021-09-22 13:51:18 -04:00
enjoy-digital 1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix 
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
 2021-09-22 19:35:47 +02:00
Florent Kermarrec 60c6077c32 remote/comm_udp: Add padding bytes to Etherbone probe. 
Now required with LiteEth dropping exceeding payload.
 2021-09-22 16:52:08 +02:00
Gabriel Somlo 23b2ac2013 cpu/vexriscv_smp/crt0.S: only boot core should run data_init 
Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
 2021-09-22 09:55:20 -04:00
Florent Kermarrec 027f7aa645 tools/litex_json2dts_linux: Fix typo. 2021-09-21 14:32:20 +02:00
Florent Kermarrec 84f1afd6d4 tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs. 
Were not useful as pointed by @shenki and @stffrdhrn.
 2021-09-21 13:37:25 +02:00
enjoy-digital b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard 
Json2dts sdcard booting
 2021-09-21 13:13:07 +02:00
Andwer E Wilson 9f75c73d6b build/xilinx/common: Fix Ultrascale SDROutput/Input. 2021-09-21 10:30:36 +02:00
enjoy-digital 233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok 
Remove rsp_payload_response_ok from Vex/CFU hookup code.
 2021-09-21 09:43:15 +02:00
Florent Kermarrec 08779202f4 build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap). 2021-09-21 08:18:06 +02:00
Tim Callahan 1be449d72b Remove rsp_payload_response_ok from Vex/CFU hookup code. 
The port has already been removed from VexRiscv (issue #1036).

Signed-off-by: Tim Callahan <tcal@google.com>
 2021-09-20 15:02:51 -07:00
Florent Kermarrec 1e24fd87d1 cores/gpio: Simplify #1035. 2021-09-20 17:34:46 +02:00
enjoy-digital 6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio 
litex_sim: optionally add GPIOTristate core
 2021-09-20 17:21:29 +02:00
enjoy-digital 0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate 
build/lattice: add DDRTristate for Crosslink-NX
 2021-09-20 14:14:40 +02:00
Florent Kermarrec 49d8000d49 gowin/common: Add Differential Input/Output support. 2021-09-20 14:14:06 +02:00
Florent Kermarrec 9c373242af gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern. 2021-09-20 11:47:32 +02:00
Maciej Kurc 6c0a758468 Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:02:01 +02:00
Florent Kermarrec 5519d908e8 cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k). 2021-09-20 09:29:05 +02:00
Florent Kermarrec 4fe085cc1c cores/clock: Add initial GW1NSR's PLL support. 2021-09-20 08:39:25 +02:00
Florent Kermarrec 76c782c546 inetgration/builder: Check for full software re-build only when a CPU is used. 2021-09-20 08:31:22 +02:00
Florent Kermarrec 46cd9c5a5c tools: Minor #1030 cleanups. 2021-09-17 14:37:48 +02:00
Florent Kermarrec 8ccb1a91c9 build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available. 2021-09-17 14:37:14 +02:00
enjoy-digital 24f0432253
Merge pull request #1030 from teknoman117/fix-lxserver-pcie-crossover 
Fixes to allow crossover uart over PCIe with lxterm and litex_server
 2021-09-17 14:28:25 +02:00
enjoy-digital a7c9e4ed42
Merge pull request #1033 from caverar/patch-1 
Linker fix for initialized global variables
 2021-09-17 14:23:44 +02:00
Florent Kermarrec 7f8e2e39f3 cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes. 2021-09-16 18:56:05 +02:00
Pawel Sagan e8e14d8ca5 build/lattice: add DDRTristate for Crosslink-NX 2021-09-16 14:23:02 +02:00
Michal Sieron f2a05e92fa Add missing include to or1k/exception.c 2021-09-16 10:44:09 +02:00
Michal Sieron 3d4a64e112 Update stdio code in libc 
Picolibc now requires to create stdin, stdout and stderr files
ourselves instead of __iob array. Thus changes and renaming
of iob.c to stdio.c

f320a0aa17
added option to select default printf format, so using
picolibc.specs or defining PRINTF_LEVEL is no longer needed.
 2021-09-16 10:44:07 +02:00
Michal Sieron ef7b287248 Disable thread local storage (TLS) in picolibc 
It was causing some compilation issues with lm32.
As global errno was enabled anyway, it was easier 
to disable TLS whatsoever.
 2021-09-16 10:43:44 +02:00
Michal Sieron c84105f399 Disable LTO for picolibc and use picolibc.specs 
Use picolibc.specs to specify integer only printf/scanf.

To do that, we need to pass specs file with options to
the linker. With LTO enabled, name mapping was failing,
so LTO is now disabled for picolibc compilation only.

This also means, that exchange.c and arc4random.c no
longer need to be recompiled and added back.
 2021-09-16 10:43:41 +02:00
Michal Sieron 49c4ae9ec9 Add ppc64le-linux[-musl] to microwatt gcc triples 2021-09-16 10:42:54 +02:00
Michal Sieron 72e7eac0ef Fix demo compilation 2021-09-16 10:42:54 +02:00
Michal Sieron befd9c0e4c Add comment documenting libc/missing.c 2021-09-16 10:42:54 +02:00
Michal Sieron 63094205d7 Add comment documenting libc/iob.c 2021-09-16 10:42:54 +02:00
Michal Sieron c96c7f5c45 Fix machine specific directory copying 2021-09-16 10:42:54 +02:00
Michal Sieron d3c23fb048 Remove libmisc 2021-09-16 10:42:54 +02:00
Michal Sieron 7fcc094b63 Don't filter out INCLUDE flags 2021-09-16 10:42:54 +02:00
Michal Sieron cf59481567 Move machine specific code to their directories 2021-09-16 10:42:54 +02:00
Michal Sieron 66c54de785 Move sim_debug to the BIOS directory 2021-09-16 10:42:54 +02:00
Michal Sieron b960ba0a67 Move stuff out of libbase 
Removed libbase completely and moved remaining files into
libutils, libcomm and libmisc.

Libcomm is place for code used for communicating with other
devices, which doesn't yet live in its own liblite*.

Libutils is code used in multiple places, like crc calculation,
progress bar, memtests.

Libmisc is everything else like sim_debug, which is code for
litex_sim or exception.c for or1k.
 2021-09-16 10:42:54 +02:00
Michal Sieron 91ce95fb49 Remove obsolete _include/dyld_ 
As per b5048f6cf1
it was necessary by libunwind, which we aren't building.
 2021-09-16 10:42:54 +02:00
Michal Sieron 6dc4908d12 Remove obsolete _include/basec++_ 
As per 7a9975ab5a
it was necessary to build libunwind, which we aren't building.
 2021-09-16 10:42:54 +02:00