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Author SHA1 Message Date
Michal Sieron
1a1a81bfa0 Move _exit function up, so gcc doesn't complain 2021-09-16 10:42:54 +02:00
Michal Sieron
9f169d5520 Enable long long support in IO operations 2021-09-16 10:42:54 +02:00
Michal Sieron
351a0713af Remove unused base/uart.h include 2021-09-16 10:42:54 +02:00
Michal Sieron
26c5a8a926 Move libbase/id.c to bios/cmd/cmd_bios.c 2021-09-16 10:42:54 +02:00
Michal Sieron
6bff5f1734 Replace inet.h with arpa/inet.h 2021-09-16 10:42:54 +02:00
Michal Sieron
082d1231f6 Remove obsolete time.c 2021-09-16 10:42:54 +02:00
Michal Sieron
823edfad22 Remove obsolete div64.c 2021-09-16 10:42:54 +02:00
Michal Sieron
8e4e3b5438 Enable LTO 
Use gcc-ar and gcc-nm, because they have LTO plugins

Turn off LTO for libcompiler_rt, exchange.c and arc4random.c
from newlib.

Also add getentropy, dummy function, because for some reason
libbase/console.c wants it.
 2021-09-16 10:42:29 +02:00
Michal Sieron
53135eb7bc Add missing definitions if target is microwatt 
Picolibc compilation for powerpc was missing some defines.
This adds them to gcc parameters
 2021-09-16 10:41:05 +02:00
Michal Sieron
ba1d20f2ad Add missing functions to make lm32 and or1k link 
I added missing.c with functions that were preventing
LiteX from successfull linking on lm32 and or1k.
 2021-09-16 10:41:05 +02:00
Michal Sieron
4e50c0ba00 Enable global errno 
Brings mor1kx compilation to the same error as lm32
 2021-09-16 10:41:05 +02:00
Michal Sieron
ab881c561f Implement initial support for lm32 and or1k 
Picolibc doesn't maintain meson.build or cross*.txt files
for lm32 and or1k CPUs.

This commit adds meson.build files for both of them.
Also libc/Makefile got modifed to determine CPU family
from $(CPU) value and generate cross.txt file.
Now picolibc gets compiled with LiteX flags too.

It doesn't compile on neither of them yet,
but at least riscv still works.
 2021-09-16 10:41:05 +02:00
Michal Sieron
ca4e17d886 Disable float support in tinystdio 
Float support was originally disabled in libbase
 2021-09-16 10:41:05 +02:00
Michal Sieron
b34adcf929 Remove libbase-nofloat.a variant 
As vsnprintf is no longer compiled it was
identical to libbase.a.

Picolibc defines levels of printf and scanf
https://github.com/picolibc/picolibc/blob/main/doc/printf.md#printf-and-scanf-levels-in-picolibc
so those should probably be used.
 2021-09-16 10:41:05 +02:00
Michal Sieron
c4ba313b86 Remove unnecessary header and source files 2021-09-16 10:41:05 +02:00
Michal Sieron
a6094fd418 Move libbase/console.c logic to libc/iob.c 2021-09-16 10:41:05 +02:00
Michal Sieron
768961ec59 Use getchar/putchar instead of readchar/base_putchar 2021-09-16 10:41:05 +02:00
Michal Sieron
ead3f8b2e0 Compile iob.c with $(compile) 2021-09-16 10:41:05 +02:00
Michal Sieron
8a38a79967 Remove unnecessary headers 2021-09-16 10:41:05 +02:00
Michal Sieron
10927691c5 Remove base and add picolibc to include search paths 2021-09-16 10:41:05 +02:00
Michal Sieron
19966edb61 Replace putsnonl(s) with fputs(s, stdout) 
It won't compile, because stdout is undefined, but
including headers from picolibc should fix that
 2021-09-16 10:41:05 +02:00
Michal Sieron
acf3a4570b Create __iob for picolibc 
Picolibc requires __iob array for its IO functions

This commit creates such array with dummy functions
using putchar/readchar from console.c

To prevent name conflicts printf and others were
removed from console.c

Also putchar had to be renamed to base_putchar
 2021-09-16 10:41:05 +02:00
Michal Sieron
db390537a9 Compile entire picolibc 
It does not compile yet, will need __iob array to be defined
Also there are multiple definitions of some functions
 2021-09-16 10:41:05 +02:00
Michal Sieron
514754bedf Get pythondata-software-picolibc from antmicro 2021-09-16 10:41:05 +02:00
Michal Sieron
fc0fa88e33 Update litex_setup.py to use forked codebase 2021-09-16 10:41:05 +02:00
Michal Sieron
6de59bdbc0 Incorporate picolibc into the build process 
Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command

Tested with digilent_arty.py
 2021-09-16 10:41:05 +02:00
Michał Sieroń
e25ca4082b Apply patch removing need for most of libbase 2021-09-16 10:41:05 +02:00
Florent Kermarrec
05b960d09b CHANGES: Update. 2021-09-15 12:08:30 +02:00
enjoy-digital
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll 
Fix premature selection of full PLL config with no feedback
 2021-09-15 08:52:59 +02:00
George Hilliard
91ec6e0da8 clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond 
Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs.  Emit the same attributes that Diamond's PLL tool does.
 2021-09-15 00:07:43 -05:00
George Hilliard
6733a3e3e6 clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search 2021-09-15 00:07:43 -05:00
Florent Kermarrec
88d302d4db soc/alloc_region: Ensure allocated Region is aligned on size. 2021-09-14 18:08:07 +02:00
Florent Kermarrec
694878a35a integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints. 
Some boards require specific constraints, so disable them in this case and put constraints in the target file.
 2021-09-13 19:32:50 +02:00
Florent Kermarrec
cb7b0f44cf tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
Florent Kermarrec
e0e9311ceb interconnect/wishbone: Specify Wishbone version (#999). 2021-09-08 17:33:01 +02:00
Florent Kermarrec
6c2bc02323 build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names. 
This makes it similar to add_platform_command and add more flexibility to constraint the design.
 2021-09-08 16:14:58 +02:00
Florent Kermarrec
0222697f21 liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size. 
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.

This will be less accurate but will still provide representative results which
is the aim of this test.
 2021-09-08 09:10:21 +02:00
Florent Kermarrec
10c4523c32 soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY. 2021-09-07 15:09:05 +02:00
Florent Kermarrec
575af6fc60 litespi/integration: Review/Cleanup #1024. 
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
 2021-09-07 14:36:13 +02:00
enjoy-digital
aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor 
litex: adding litespi to simulation, making litespi compatible with new implementation
 2021-09-07 13:17:40 +02:00
enjoy-digital
bdd4717daa
Merge pull request #1028 from wuhanstudio/fix-syntax-error 
fix: missing colon syntax error
 2021-09-07 13:00:48 +02:00
wuhanstudio
5d9880888c fix: missing colon syntax error 2021-09-07 11:21:41 +01:00
Florent Kermarrec
a6f9ac58bb build/sim/common: Review/Cleanup #1021 for consistency with other backends. 2021-09-07 09:44:43 +02:00
enjoy-digital
2b700057b7
Merge pull request #1021 from antmicro/ddr_sim 
litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
 2021-09-07 09:38:14 +02:00
Florent Kermarrec
7c50f52a57 tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets. 
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
 2021-09-07 09:27:51 +02:00
enjoy-digital
1598b5958d
Merge pull request #1017 from asadaleem-rs/master 
customize main ram size from command line argument
 2021-09-07 09:15:55 +02:00
Florent Kermarrec
e257d91d46 cpu/vexriscv: Review/Cleanup #1022. 
Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
 2021-09-07 09:04:47 +02:00
enjoy-digital
6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache 
Restructure config flags for dcache/icache presence in Vex.
 2021-09-07 08:46:03 +02:00
Tim Ansell
bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes 
Binutils fixes
 2021-09-06 17:16:56 -07:00
Pawel Sagan
ad0fcc22e6 litex: adding legacy mode for litespi 
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
 2021-09-03 09:42:41 +02:00