21 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	204452b0d3	m1crg: make clock feedback pin bidirectional	2012-02-16 18:35:44 +01:00
Sebastien Bourdeauducq	f36a45edcb	lm32: compatibility with the new instance API	2012-02-16 18:35:22 +01:00
Sebastien Bourdeauducq	72f9af9d90	Generate all clocks for the DDR PHY	2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq	859c9d8849	Use new bus API	2012-02-15 16:55:13 +01:00
Sebastien Bourdeauducq	506ffab11a	uart: RX support	2012-02-07 14:12:23 +01:00
Sebastien Bourdeauducq	58f4f78d2c	sram: fix sub-word write	2012-02-06 23:13:35 +01:00
Sebastien Bourdeauducq	5dc875de69	UART: use new bank API and event manager	2012-02-06 17:45:31 +01:00
Sebastien Bourdeauducq	b5cb1083ab	sram: fix WE signal	2012-02-03 10:38:17 +01:00
Sebastien Bourdeauducq	8a2646a549	Remove explicit bus names	2012-01-27 22:21:08 +01:00
Sebastien Bourdeauducq	28f00c3a9a	Add on-chip SRAM	2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq	6fde54c5aa	Use meaningful class names	2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq	f8d5c27ef8	Wishbone: omit fixed LSBs	2012-01-13 17:28:58 +01:00
Sebastien Bourdeauducq	b60abfaa4a	Convert -> convert	2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq	3b640c45bb	Use new syntax	2011-12-18 22:02:05 +01:00
Sebastien Bourdeauducq	6664af73d1	uart: new design using FHDL and bank (TX only, incomplete)	2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq	bb21f7584a	32-device, 8-bit CSR bus	2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq	85fbe07b94	clkfx module	2011-12-17 15:00:11 +01:00
Sebastien Bourdeauducq	411e1af980	Proper reset generation	2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq	738b45dcbd	Support the new FHDL syntax	2011-12-16 21:30:22 +01:00
Sebastien Bourdeauducq	ca68097ef6	Pay a bit more attention to PEP8	2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq	b487e99bcf	Initial import	2011-12-13 17:33:12 +01:00