Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
3,937 Commits 40 Branches 14 Tags 26 MiB
Commit Graph

3937 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq efb2466c7e gensoc: add id for KC705 2014-08-06 23:53:51 +08:00
Sebastien Bourdeauducq fb48b89bac platforms/kc705: generate clocks for SDRAM 2014-08-06 23:53:26 +08:00
Sebastien Bourdeauducq 7ebf08db5e mibuild/xilinx: connect CE on reset synchronizer FFs 2014-08-06 23:51:50 +08:00
Sebastien Bourdeauducq b124a98d92 genlib: add reset synchronizer 2014-08-06 19:38:37 +08:00
Sebastien Bourdeauducq ca6d6954c1 targets/ppro: use migen reset synchronizer 2014-08-06 19:38:11 +08:00
Sebastien Bourdeauducq 4d382328d5 mibuild/xilinx: share more code between ISE and Vivado, use special overrides with Vivado, merge xilinx_tools into xilinx_common 2014-08-06 19:26:00 +08:00
Florent Kermarrec d1ff43faa7 gensoc/cpuif: do not generate access functions for registers > 64 bits 2014-08-04 22:38:19 +08:00
Florent Kermarrec 452a4a76f3 use verilog namespace to export mila configuration 2014-08-03 17:09:01 +02:00
Sebastien Bourdeauducq 37968e649b targets/kc705: use PLL for clocking 2014-08-03 21:42:39 +08:00
Florent Kermarrec 6ffed70b59 uart2wishbone: disconnect rx line from shared pads when bridge is selected 
(avoid CPU crash when we communicate with the bridge)
 2014-08-03 13:15:56 +02:00
Sebastien Bourdeauducq 8a7afff30a platforms/kc705: fix speed grade 2014-08-03 17:51:44 +08:00
Florent Kermarrec f4e6cebab2 clean up 2014-08-03 11:44:27 +02:00
Sebastien Bourdeauducq 1a09eb7a19 mor1kx: sync 2014-08-03 15:57:55 +08:00
Sebastien Bourdeauducq 8adf6027e1 platforms/kc705: add automatic clk200 constraint 2014-08-03 15:53:58 +08:00
Sebastien Bourdeauducq 40dcc8b2aa platforms/kc705: use XC3SProg 2014-08-03 15:53:42 +08:00
Sebastien Bourdeauducq 210cb720c1 platforms/kc705: use Vivado by default 2014-08-03 15:53:21 +08:00
Sebastien Bourdeauducq 536a220679 mibuild/programmer: fix XC3SProg init 2014-08-03 15:52:34 +08:00
Sebastien Bourdeauducq 61eae462f3 README: update 2014-08-03 15:48:55 +08:00
Sebastien Bourdeauducq f7a7137127 targets: add basic KC705 2014-08-03 15:48:30 +08:00
Sebastien Bourdeauducq 213cb43ae5 Keep only basic SoC designs in MiSoC 2014-08-03 12:30:15 +08:00
Florent Kermarrec cd51e78f54 storage: use SyncFIFOBuffered to implement fifo in block ram 2014-08-02 19:12:03 +02:00
Florent Kermarrec a0d0742664 mibuild/generic_platform: add recursive parameter to add_source_dir 2014-08-02 21:25:51 +08:00
Sebastien Bourdeauducq 8baa957539 genlib/fifo: use synchronous memory read instead of additional register 
The latter causes problems with InsertReset
 2014-08-02 08:52:49 +08:00
Florent Kermarrec 47a85cc1ad use new MiSoC fifo (no flush signal) 2014-08-01 10:36:15 +02:00
Sebastien Bourdeauducq 9395214d75 remove stale programmer.py 2014-08-01 12:34:38 +08:00
Florent Kermarrec 62c9043d07 move programmer to mibuild 2014-08-01 08:03:53 +08:00
Florent Kermarrec 82068267db mibuild: move programmer to mibuild and create programmer directly in platforms 2014-08-01 08:03:36 +08:00
Florent Kermarrec 25b3aff6f1 sdramphy: add init sequence for DDR3 2014-07-31 10:29:32 +08:00
Yann Sionneau 32171da46d Better UART baudrate generator, and testbench 
This enables high speed (tested to 4Mbps) operation.
 2014-07-31 10:24:52 +08:00
Sebastien Bourdeauducq 244ee52381 kc705/ddram: use lighter pin syntax 2014-07-30 10:31:26 +08:00
Florent Kermarrec 9cf204598a mibuild/xilinx_vivado: allow sharing Misc constraints with ISE: example: ISE: DIFF_TERM=True VIVADO: set property DIFF_TERM TRUE 2014-07-30 10:10:41 +08:00
Sebastien Bourdeauducq 2cb7d73870 mor1kx: sync 2014-07-28 21:36:00 -06:00
Florent Kermarrec 84eb146e0a kc705: add ddram pins 2014-07-28 21:35:18 -06:00
Robert Jordens fe1c4535d0 mibuild.xilinx_vivado: support settingsXX.sh 
* in the process refactor the version search, the architecture bit width
 detection, the settings search and all also for xilinx_ise
* use distutils.version.StrictVersion
 2014-07-27 19:50:15 -06:00
Robert Jordens 44c6e524ba migen.fhdl.structure: add Signal.like(other) 
This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
 2014-07-24 23:52:59 -06:00
Florent Kermarrec 9fcea6e64a migen/sim/generic: use kwargs to pass parameters to icarus.Runner 2014-07-24 10:17:54 -06:00
Robert Jordens 10d639d313 flow.plumbing: spelling 2014-07-19 14:29:51 -06:00
Robert Jordens 9266e10cae flow.plumbing: make argument order consistent 2014-07-19 14:29:50 -06:00
Sebastien Bourdeauducq ff1d105c7e genlib/SyncFIFO: remove flush signal (use InsertReset instead) 2014-07-17 19:15:45 -06:00
Fabien Marteau a53feba8a1 mibuild/platforms: add APF27 and APF51 Armadeus platforms 2014-07-11 11:07:54 -06:00
Fabien Marteau f45897c97f mibuild/generic_platform.py: adding ability to use void pins (none fpga pin) for connectors 
Signed-off-by: Fabien Marteau <fabien.marteau@armadeus.com>
 2014-07-09 10:41:51 +02:00
Sebastien Bourdeauducq 8349543732 style 2014-07-05 18:56:20 +02:00
Sebastien Bourdeauducq 2bb821c571 crt-or1k: trim useless exception vectors 2014-07-05 18:53:23 +02:00
Sebastien Bourdeauducq 9a64309fcd Merge branch 'master' of github.com:m-labs/misoc 2014-07-04 10:29:53 +02:00
Sebastien Bourdeauducq 6462ee7fe1 Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable. 2014-07-04 10:29:42 +02:00
Florent Kermarrec d4833cb3dc cpuif: remove limitations on csr data_width 2014-06-28 17:39:55 +02:00
Sebastien Bourdeauducq 506ac0f780 Merge branch 'master' of github.com:m-labs/migen 2014-06-28 16:15:20 +02:00
Florent Kermarrec f6dfabf7a9 mibuild/xilinx_vivado.py: add set property to misc constraint 2014-06-28 16:15:07 +02:00
Florent Kermarrec a0df5baa55 host: add support for various csr_data width (8 & 32 tested, but should work with others) 2014-06-26 13:22:21 +02:00
Sebastien Bourdeauducq af9f76f73a Merge branch 'master' of github.com:m-labs/migen 2014-06-22 15:34:02 +02:00