Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,095 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

4095 Commits

Author SHA1 Message Date
Florent Kermarrec 69f0035315 gen/fhdl: add Display for debug in simulation 2016-04-29 23:03:43 +02:00
Florent Kermarrec e79b2e3fef boards/targets: SDRAM modules are now litedram.modules 2016-04-29 19:05:23 +02:00
Florent Kermarrec 3d71ba6e66 targets: remove sdram_controller_type parameter (minicon removed) 2016-04-29 17:51:16 +02:00
Florent Kermarrec 8c7332e75e soc/integration/soc_sdram: use new LiteDRAM names 2016-04-29 17:40:55 +02:00
Florent Kermarrec dc52d33fba soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage) 2016-04-29 16:24:24 +02:00
Florent Kermarrec 44d766c09f software/sdram: cleanup artix7 init 2016-04-29 15:55:10 +02:00
Florent Kermarrec 5fb0fe925e setup.py: fix version (0.1) 2016-04-29 14:39:14 +02:00
Florent Kermarrec 66362b1280 move sdram code to litedram (https://github.com/enjoy-digital/litedram) 2016-04-29 07:45:15 +02:00
Florent Kermarrec 42767286ca gen/fhdl/verilog: add do in reserved_keywords 2016-04-27 17:43:25 +02:00
Florent Kermarrec 80d673e502 soc/integration/soc_sdram: always generate L2_SIZE constant 2016-04-27 12:34:18 +02:00
Florent Kermarrec 4e451a78d6 soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually) 2016-04-27 12:33:44 +02:00
Florent Kermarrec ab8569916b boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits 2016-04-26 23:29:35 +02:00
Florent Kermarrec e6681bbb9c soc/interconnect/wishbone: add FlipFlop (should be removed) 2016-04-25 19:14:20 +02:00
Florent Kermarrec b6d8999471 platforms/arty: add missing address pins, was not going to work :( 2016-04-25 16:56:23 +02:00
Florent Kermarrec f6e1c45d57 gen/genlib/record: fix connect 2016-04-21 19:05:01 +02:00
Florent Kermarrec e80cfedd7f gen/genlib/record: fix connect 2016-04-21 12:16:26 +02:00
Florent Kermarrec 9ae16c2f40 boards/platforms/nexys_video: use TDMS_33 on hdmi 2016-04-21 11:13:29 +02:00
Florent Kermarrec 3d98be0997 use new Record.connect omit parameter (replace leave_out) 2016-04-21 09:39:21 +02:00
Florent Kermarrec c330e7be49 gen/genlib/record: rename leave_out by omit and add keep parameter to Record.connect 2016-04-21 09:39:12 +02:00
Florent Kermarrec ee378b2557 boards/plaforms/nexys_video: fix hdmi_out pinout 2016-04-19 19:04:05 +02:00
Florent Kermarrec 849434c1bd soc/software/bios: show cpu on first banner line 2016-04-19 09:19:37 +02:00
enjoy-digital 76bb0ef456 Merge pull request #2 from mithro/master 
More fixes.
 2016-04-19 09:07:23 +02:00
Florent Kermarrec 1b9ab2f1fc soc/integration/cpu_interface: fix clang detection 2016-04-19 08:06:56 +02:00
Tim 'mithro' Ansell d9b598368f Make verilator build output error messages. 2016-04-19 16:02:26 +10:00
Tim 'mithro' Ansell 8998ae5c92 bios: Print CPU architecture on boot. 2016-04-19 16:02:26 +10:00
enjoy-digital e0e56e3655 Merge pull request #1 from mithro/master 
Bunch of small fixes
 2016-04-19 07:49:24 +02:00
Tim 'mithro' Ansell 514496d744 libcompiler_rt: Fixing Makefile for CPU endianness. 2016-04-19 14:55:01 +10:00
Florent Kermarrec 5ba03160ed soc/cores: fix spi 2016-04-19 06:49:23 +02:00
Florent Kermarrec 7b7f1dd68c Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-19 06:05:22 +02:00
Tim 'mithro' Ansell e7f3c585b7 Allow using gcc for or1k. 
* Using CLANG can set by using CLANG=1 or CLANG=0 in the environment.
 * or1k continues to default to CLANG if environment is not net.
 2016-04-19 14:03:24 +10:00
Tim 'mithro' Ansell 2f834d0aa2 bios: Use single characters for boot modes. 
* The function keys never really worked properly.
 * Also add commands for the ROM/Flash/etc.
 2016-04-19 13:42:56 +10:00
Florent Kermarrec 429f533bd0 soc/cores/sdram/settings: simplify modules and fix timing margins computation 2016-04-18 18:22:53 +02:00
Florent Kermarrec 41f6408d56 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-15 08:09:42 +02:00
Florent Kermarrec 7b3699839e build/xilinx/ise: use Tim's fix on add_period_constraint and add_false_path_constraint 2016-04-14 21:48:52 +02:00
Florent Kermarrec 3d222d9e63 soc/interconnect/dma_lasmi: change endpoint names 2016-04-13 18:28:52 +02:00
Florent Kermarrec fcd8d792a1 Merge branch 'master' of https://github.com/enjoy-digital/litex 2016-04-13 01:19:21 +02:00
Florent Kermarrec 6e0045e6be soc/integration/soc_sdram: allow passing controller settings in register_sdram 2016-04-12 20:16:47 +02:00
Florent Kermarrec 40eb779e67 software/include/base: fix system.h for or1k 2016-04-10 17:21:54 +02:00
Florent Kermarrec 238d69f186 software/common: use -std=gnu99 for GCC 2016-04-10 17:21:17 +02:00
Florent Kermarrec b2eaf412c1 soc/interconnect/stream/PipelinedActor: add latency attribute 2016-04-07 12:10:32 +02:00
Florent Kermarrec 9fa9bdcf68 build/sim: adapt verilator simulation to new stream signals 2016-04-07 08:56:53 +02:00
Florent Kermarrec 8ced064160 soc/software/libcompiler_rt: fix mulsi3 compilation 2016-04-07 08:28:38 +02:00
Florent Kermarrec 80d78698e3 soc/software/libnet/microudp: fix debug flag 2016-04-07 08:28:38 +02:00
Florent Kermarrec 454d5d13e2 soc/software: fix libcompiler_rt mulsi3.c compile 2016-04-04 08:36:23 +02:00
Florent Kermarrec 17f6cb1f17 initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush) 2016-04-01 00:09:17 +02:00
Florent Kermarrec 7e62cdf601 soc/software/bios: update default ip addresses (local: 192.168.1.50 / remote: 192.168.1.100) 2016-03-31 10:55:11 +02:00
Florent Kermarrec 1d4f44e7db soc/interconnect/stream_sim: add more genericity to PacketStreamer/PacketLogger to use them for all cores 2016-03-31 00:02:22 +02:00
Florent Kermarrec b8d89535fd soc/cores/sdram/phy: fix S6QuarterRateDDRPHY 2016-03-29 14:59:30 +02:00
Florent Kermarrec 7cd83c420f README: update 2016-03-28 23:05:16 +02:00
Florent Kermarrec f512971d9e gen/sim: hack to update vcd output file during simulation (allow visualizing progress directly and having a vcd file even when simulation fails or doesn't stop) 2016-03-25 13:22:26 +01:00