991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
7c058a52c9
com/spi: use .format in tb
2015-03-03 10:44:05 +01:00
0716dadaf2
targets: keep the SPI flash core even if with_rom is enabled, so that flash booting in the BIOS still works
2015-03-03 10:39:31 +01:00
1d4dc45436
LiteXXX cores: use format in prints
2015-03-03 10:29:28 +01:00
f27e7a4b22
litesata: remove unneeded clock constraint
2015-03-03 10:24:05 +01:00
0bcd6daf63
soc: remove is_sim function
2015-03-03 10:15:11 +01:00
905be50451
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
2015-03-03 09:55:25 +01:00
9210272356
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
2015-03-03 09:23:21 +01:00
2f7206b386
sdram: revert use of scalar values for DFIInjector
2015-03-03 09:09:54 +01:00
9df60bf98e
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
2015-03-03 09:02:53 +01:00
f154c2e7ec
xilinx/programmer/vivado: fix Linux support
2015-03-03 02:06:39 +00:00
154ad54a8e
platforms/kc705: fix imports
2015-03-03 02:03:14 +00:00
ff29c86fe1
litesata/kc705: use FMC pin names
2015-03-03 01:02:50 +00:00
8e48502d03
spiflash: style
2015-03-03 00:54:30 +00:00
2513833a24
README: 80 columns
2015-03-03 00:17:34 +00:00
69a0c597ad
make.py: use ternary getattr
2015-03-02 23:54:00 +00:00
a56fce045b
Merge branch 'master' of http://github.com/m-labs/migen
2015-03-02 23:24:48 +01:00
29c5bb8bcd
mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default)
2015-03-02 23:23:23 +01:00
36f4b68dd8
mibuild/sim: style fixes
2015-03-02 21:56:20 +00:00
410a162841
sdram: disable by default bandwidth_measurement on lasmicon
2015-03-02 19:53:16 +01:00
ca42611b6b
README: add Pipistrello
2015-03-02 19:18:46 +01:00
3449b7c933
update README
2015-03-02 18:41:03 +01:00
02ef1dc95a
targets: fix mlabs_video FramebufferSoC
2015-03-02 18:38:43 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
3465db25a7
soc/sdram: be more generic in naming
2015-03-02 11:55:28 +01:00
97331153e0
sdram: create core dir and move lasmicon/minicon in it
2015-03-02 11:38:22 +01:00
de698c51e4
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
2015-03-02 11:29:43 +01:00
6b24562eea
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
2015-03-02 10:59:43 +01:00
0980becb56
sdram: improve memtest by adding 2 different writes/reads
...
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
46020fd253
sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
2015-03-02 10:34:29 +01:00
c0b38e4905
sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
2015-03-02 09:18:32 +01:00
7300879b7f
sdram: move dfii to phy
2015-03-02 09:08:28 +01:00
9ad05b21ca
sdram: fix remaining data_valid in dma_lasmi
2015-03-02 09:05:18 +01:00
88e7fa21e4
sdram: create test dir and move lasmicon/minicon tests to it
2015-03-02 08:42:55 +01:00
b305b7828a
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
2015-03-02 08:36:39 +01:00
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
6d83a112e6
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:27 +01:00
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
382ca374c3
mibuild: initial Verilator support
2015-03-01 18:27:46 +01:00
f58394f6af
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
2015-03-01 18:25:47 +01:00
4f37d29d05
flash/spi: make bitbang optional (enabled by default)
2015-03-01 17:15:22 +01:00
096e95cb59
uart: use data instead of d on endpoint's layouts (coherency with others cores)
2015-03-01 16:56:48 +01:00
1e6d1deae8
uart: add sim phy
2015-03-01 16:52:50 +01:00
649cdeb265
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
8f81ae6826
genlib/misc: add FlipFlop, Counter, Timeout
2015-03-01 16:33:46 +01:00
bd4d3cd73b
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
2015-03-01 12:14:34 +01:00
9e01bf5fdd
litesata: create example design derived from SoC
2015-03-01 11:33:38 +01:00
c21a7956c8
liteXXX cores: remove Identifier duplication
2015-03-01 11:24:58 +01:00
67ca0da1d9
liteXXX cores: share same methodology for on-board tests
2015-03-01 11:21:12 +01:00
Florent Kermarrec
Sebastien Bourdeauducq