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6,342 Commits 40 Branches 14 Tags 51 MiB
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6342 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 6a979a8023 mibuild: sanitize default clock management 2015-03-14 00:10:08 +01:00
Sebastien Bourdeauducq 702d177c85 mibuild: get rid of Platform factory function, cleanup 2015-03-13 23:25:15 +01:00
Sebastien Bourdeauducq 32676fffd2 soc/sdram: sync with new mibuild toolchain management 2015-03-13 23:19:08 +01:00
Florent Kermarrec c3c7f627d9 liteeth/phy: typo (thanks sb) 2015-03-12 21:54:10 +01:00
Florent Kermarrec ff266bc2ee migen/genlib/io: add DifferentialOutput and Xilinx implementation 2015-03-12 19:30:57 +01:00
Florent Kermarrec bf28664cb4 genlib/io.py: fix copy/paste error (thanks rjo) 2015-03-12 18:49:49 +01:00
Florent Kermarrec c8ba8cde8e migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild 2015-03-12 18:38:53 +01:00
Florent Kermarrec 1b72b81f9c targets/simple: use new generic DifferentialInput 2015-03-12 18:36:04 +01:00
Florent Kermarrec f18ae9b9fe targets/simple: insert IBUFDS for Xilinx devices (not implemented for others vendors) 2015-03-12 17:25:01 +01:00
Florent Kermarrec cd6c04b24f soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx 2015-03-12 17:12:56 +01:00
Florent Kermarrec 767d45727a uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty). 2015-03-12 16:57:38 +01:00
Florent Kermarrec 00e8616de2 mibuild/sim: clean up (thanks sb) 2015-03-10 16:41:52 +01:00
Sebastien Bourdeauducq 555c444da2 mibuild/sim/dut_tb: fix permissions 2015-03-10 11:06:55 +01:00
Florent Kermarrec 9d8f1cd61d mibuild/sim: get serial dev from /tmp/simserial 2015-03-10 00:42:54 +01:00
Florent Kermarrec 70a3e8081c mibuild/sim: add support for pty 2015-03-09 23:31:11 +01:00
Florent Kermarrec b157031e8a uart/sim: add pty (optional, to use flterm) 2015-03-09 23:29:06 +01:00
Florent Kermarrec 6cbf13036b liteeth/mac: fix padding limit (+1), netboot OK with sim platform 2015-03-09 20:59:34 +01:00
Florent Kermarrec aa609bee15 mibuild/sim: remove hack, the issue was in gateware (padding) 2015-03-09 20:57:20 +01:00
Florent Kermarrec 47cceea222 liteeth/mac: use Counter in sram and move some logic outside of fsms 2015-03-09 20:22:14 +01:00
Florent Kermarrec 8e09a86e4f genlib/misc: add increment parameter to Counter 2015-03-09 20:20:25 +01:00
Florent Kermarrec ebcea3c000 fhdl/module: use r.append() in _collect_submodules 2015-03-09 19:45:02 +01:00
Florent Kermarrec b10836a8eb liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit 2015-03-09 17:21:29 +01:00
Florent Kermarrec 1b58813d13 soc: do_exit is now provided by modules 2015-03-09 17:18:42 +01:00
Florent Kermarrec ee1091f491 fhdl/module: avoid flushing self._submodules and create do_exit. 2015-03-09 17:17:21 +01:00
Florent Kermarrec efc5f221d9 mibuild/sim: clean up and move eth struct to sim 2015-03-09 14:40:33 +01:00
Florent Kermarrec a72c091bc2 mibuild/sim: regroup console_tb/ethernet_tb in dut_tb 2015-03-09 14:40:31 +01:00
Florent Kermarrec e82b540a96 mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up 2015-03-09 13:30:21 +01:00
Robert Jordens 3e84c66ba9 vivado: permit resources without pins 
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
 2015-03-09 13:30:19 +01:00
Florent Kermarrec 360c849f21 liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter) 2015-03-09 13:23:39 +01:00
Florent Kermarrec 5dbd8af4be liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap 2015-03-09 13:23:37 +01:00
Florent Kermarrec e60a97534b mibuild/sim: able to visualize arp requests with wireshark 
now need to find why that is not responding...
 2015-03-06 20:16:30 +01:00
Florent Kermarrec a64acdfa65 mibuild/sim: able to send ethernet frame from sim to server.py 2015-03-06 12:49:56 +01:00
Florent Kermarrec 0029b87628 mibuild/sim: add ethernet pins to verilor.py 2015-03-06 12:20:17 +01:00
Florent Kermarrec d20b9c2221 uart: pass *args, **kwargs to sim phy 2015-03-06 12:08:10 +01:00
Florent Kermarrec 658d4d4c49 platforms/sim: add ethernet pins 2015-03-06 10:20:26 +01:00
Florent Kermarrec af66ca7bad uart: add phy autodetect function 2015-03-06 10:19:29 +01:00
Florent Kermarrec e133777450 targets/simple: add MiniSoC 2015-03-06 10:10:58 +01:00
Florent Kermarrec 95fa753149 liteeth: add phy autodetect function (phy can still be instanciated directly) 2015-03-06 10:10:34 +01:00
Florent Kermarrec bee8ccf6c7 soc: enforce cpu_reset_address to 0 when with_rom is True 2015-03-06 08:21:16 +01:00
Florent Kermarrec 2b9397ff5b targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True) 2015-03-06 07:56:45 +01:00
Sebastien Bourdeauducq 7b00141a0c genlib/cordic: fix typos 2015-03-06 00:47:23 +01:00
Florent Kermarrec 06f3c46e35 genlib/misc: fix missing *args in Counter 2015-03-04 23:49:15 +01:00
Florent Kermarrec 52f1c45407 LiteXXX cores: fix test_reg.py 2015-03-04 23:13:14 +01:00
Sebastien Bourdeauducq 60e87f6e87 Merge branch 'master' of https://github.com/m-labs/misoc 2015-03-04 00:46:41 +00:00
Sebastien Bourdeauducq 073641faa1 litesata: fix permissions and imports 2015-03-04 00:46:24 +00:00
Florent Kermarrec 200791c81d uart: generate ack for rx (serialboot OK with sim) 2015-03-04 00:57:37 +01:00
Florent Kermarrec 3d7f9fd685 mibuild/sim/server_tb: use SERIAL_SINK_ACK 2015-03-04 00:55:35 +01:00
Florent Kermarrec 2d6fbd7902 mibuild/sim: use /tmp/simsocket sockaddr for server 2015-03-03 22:52:28 +01:00
Florent Kermarrec f4b060f6fe mibuild/sim: avoid updating end at each cycle (simulation speedup) 2015-03-03 18:01:14 +01:00
Florent Kermarrec 5ec26a49c3 mibuild/sim: simplify console_tb with sim struct 2015-03-03 17:57:58 +01:00