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9406 Commits

Author SHA1 Message Date
Florent Kermarrec 8e440dc9ea soc/integration: Add LiteXSocArgumentParser to be able to expose CPU parameters to user on targets. 
Currently used for CPU parameters could problably be extented to simplify other parts
of the code in the future.
 2022-03-21 16:57:14 +01:00
Florent Kermarrec 6ef96b17bc soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr). 2022-03-21 15:21:08 +01:00
Dolu1990 f5d4977dde
Merge pull request #1246 from gsomlo/gls-memtest-cast-warning 
bios/memtest: fix cast warning
 2022-03-20 21:09:36 +01:00
Gabriel Somlo e5a2305269 bios/memtest: fix cast warning 2022-03-20 14:30:16 -04:00
developandplay 884ee45c28 Fix compilation of demo.bin on Rocket 
- Adjust memory model to fix `relocation truncated` errors
- Make isr.c shared between BIOS and demo to resolve dep on `plic_init`

Based on: https://github.com/enjoy-digital/litex/issues/1168
 2022-03-20 15:39:13 +01:00
Dolu1990 f565bec7f1 cpu/naxriscv fix xlen not being hashed, improve RV64 performances 2022-03-18 15:39:58 +01:00
Florent Kermarrec 58549834ec tools/litex_sim: Use new get_boot_address function. 
Allow litex_sim to use similar .json files than the ones used on hardware.
 2022-03-17 17:46:27 +01:00
Florent Kermarrec 4036c75600 integration/common: Add get_boot_address to get CPU boot address from json file. 
Will allow litex_sim to use similar .json files than the ones used on hardware.
 2022-03-17 17:45:30 +01:00
Florent Kermarrec dd7709ed6f tools/litex_sim/add_sdram: origin no longer required. 2022-03-17 16:47:02 +01:00
Florent Kermarrec 05724d9fea cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents. 
Avoid doing it in Linux-on-LiteX-Vexriscv.
 2022-03-17 16:28:25 +01:00
Florent Kermarrec b4db2a3ef2 tools/litex_sim: Remove obsolete max_sdram_size parameter. 2022-03-17 16:14:26 +01:00
Florent Kermarrec 3b4a885366 cpu/naxriscv/vexriscv_smp: Also enforce UART/Timer0 IRQs. 
Avoid doing it in Linux-on-LiteX-Vexriscv and allow generating bitstreams directly from litex-boards.
 2022-03-17 16:10:34 +01:00
Florent Kermarrec e6e3a909f2 cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility. 
This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards.
 2022-03-17 16:00:05 +01:00
Florent Kermarrec 2ec0ebe40f build/gowin: Add copy of bitstream to from impl to gateware directory. 2022-03-17 09:35:34 +01:00
Florent Kermarrec 148324862a integration/builder: Add get_bios_filename/get_bitstream_filename methods to simplify targets/projects. 2022-03-17 09:19:41 +01:00
Florent Kermarrec e6a81ec2af integration/soc/add_etherbone: Set default buffer_depth to 16 (Allow LiteScope's width up to 512-bit). 2022-03-16 16:43:28 +01:00
Florent Kermarrec 371608712f litex_client: Add CSR Filter. 2022-03-16 10:59:47 +01:00
Florent Kermarrec 488a6d7256 litex_client/gui: Minor changes. 
- By default, always on top.
- Update register on enter.
- Add title to viewport.
 2022-03-16 09:39:04 +01:00
Florent Kermarrec 1b128804ae tools/litex_client: Add initial and very simple GUI support. 2022-03-15 19:19:01 +01:00
Dolu1990 4896527e6f cpu/naxriscv fix git and add RV64 support (--xlen 64) 2022-03-15 11:54:28 +01:00
enjoy-digital 7712c8a79f
Merge pull request #1236 from gregdavill/trellis_compress_default 
build/trelis: Compress bitstream by default
 2022-03-11 21:56:41 +01:00
Florent Kermarrec 43cc2ff9bb software/libbase/memtest: Skip memtest_addr when size < 16KB. 2022-03-11 15:28:34 +01:00
Florent Kermarrec c851e74e09 README: Add link to new LiteX quick tour/overview presentation. 2022-03-10 18:13:44 +01:00
Florent Kermarrec 1ebcc03a92 soc/add_pcie: Add address_width support for 64-bit addressing. 2022-03-10 16:09:18 +01:00
Greg Davill 3de88c1aed build/trelis: Compress bitstream by default 2022-03-10 13:51:14 +10:30
Florent Kermarrec f446415f68 cpu/minerva: nMigen -> Amaranth. 2022-03-09 11:00:50 +01:00
Florent Kermarrec 9d5bf70cb2 cpu/femtorv/firev: Remove debug displays now that validated in sim and hardware. 2022-03-09 10:54:05 +01:00
Florent Kermarrec ece286b15d litex_setup: Rename --status to --freeze and generate freezed git_repos dict. 2022-03-08 18:12:11 +01:00
Florent Kermarrec 7411109f4d gowin/programmer: Fix copyright year. 2022-03-08 17:25:27 +01:00
enjoy-digital 72576c87fc
Merge pull request #1234 from curliph/master 
for windows/(powershell and WSL) support
 2022-03-08 17:23:05 +01:00
curliph 700077e4a1 powershell and WSL support 2022-03-08 13:52:03 +08:00
curliph cfab857c7b win/powershell support. 
add gowin programmer support.
 2022-03-08 13:16:01 +08:00
Florent Kermarrec 7ebc7625d5 tools/litex_client: Add --csr-csv support. 
Useful to debug multi-FPGA projects.
 2022-03-07 11:42:32 +01:00
Florent Kermarrec 87d5d7c87c cpu/firev/core: Review/Cleanup pass, also fix set_reset_address. 2022-03-04 12:12:06 +01:00
enjoy-digital ea883909b5
Merge pull request #1232 from sylefeb/silice-firev 
Silice FireV
 2022-03-04 11:41:13 +01:00
Florent Kermarrec 8ade60a55d soc/reset: Change the way crg_rst is set to allow possible multiple assignation in the code. 
This allows user's cores to also exercise the CRG rst with code similar to:
self.comb += If(<rst_condition>, self.crg.rst.eq(1))
 2022-03-04 10:47:52 +01:00
sylefeb 2d40846c34
Merge branch 'enjoy-digital:master' into silice-firev 2022-03-03 21:41:21 +01:00
enjoy-digital 7fcecf437a
Merge pull request #1230 from antmicro/add-cpus-to-litex_json2renode 
Add CPUs to litex_json2renode script
 2022-03-03 17:33:43 +01:00
Florent Kermarrec b092d2a180 cores/jtag: Fix chain parameter on XilinxJTAG. 2022-03-03 16:45:20 +01:00
Florent Kermarrec e00eafd97f cores/ram: Add Xilinx Ultrascale+ HBM2 wrapper. 2022-03-03 16:33:05 +01:00
Sylvain Lefebvre f5f0937493 added firev CPU 2022-03-03 15:07:38 +01:00
Michal Sieron c3fb321532 tools/litex_json2renode: Add support for Minerva 2022-03-03 12:04:33 +01:00
Michal Sieron d86bdb71ec tools/litex_json2renode: Don't use generic RV32 for Ibex 2022-03-03 12:03:03 +01:00
Michal Sieron 35dd5554ba tools/litex_json2renode: Add cv32e40p support 2022-03-03 11:59:26 +01:00
enjoy-digital 46361db135
Merge pull request #1229 from smunaut/jtag-zynq-usp 
cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
 2022-03-02 21:56:03 +01:00
Sylvain Munaut d8df6cb27d cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+ 
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2022-03-02 14:12:18 +01:00
Florent Kermarrec 4bc1691487 soc/cores/xadc: Update copyrights. 2022-03-01 14:48:02 +01:00
Florent Kermarrec 0a40616df9 litex_setup.py: Remove LiteHyperBus dependency (not currently used by LiteX-Boards). 
We could add it back as a dependency if the simple/portable core is no longer enough for
regular use cases.
 2022-03-01 09:27:23 +01:00
Florent Kermarrec dbde036162 soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus. 
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
 2022-03-01 09:11:55 +01:00
enjoy-digital 6c93db0f14
Merge pull request #1228 from sergachev/master 
Minor fixes
 2022-02-28 11:01:02 +01:00