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9034 Commits

Author SHA1 Message Date
enjoy-digital 2d1072bd67
Merge pull request #1627 from trabucayre/CC_PLL 
soc/cores/clock: adding CologneChip CC_PLL
 2023-10-05 08:16:55 +02:00
enjoy-digital ffc38c0e7c
Merge pull request #1617 from trabucayre/colognechip 
build: adding colognechip toolchain
 2023-10-05 08:16:11 +02:00
Gwenhael Goavec-Merou 1370f503e8 build: adding colognechip toolchain 
Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
 2023-10-04 22:05:32 +02:00
Gwenhael Goavec-Merou 5fd5195a7d soc/cores/clock: adding CologneChip CC_PLL 2023-10-04 22:00:53 +02:00
Florent Kermarrec c0d3766596 build/xilinx/vivado: Add pre_optimize_commands. 2023-10-03 17:24:01 +02:00
Gwenhael Goavec-Merou ca43b00337 build/efinix/common: adding Trion support for DifferentialOutput/DifferentialInput 2023-10-03 07:00:47 +02:00
Gwenhael Goavec-Merou be655f556a build/efinix/ifacewriter: fixed generate_lvds to support trion family 2023-10-03 07:00:00 +02:00
Gwenhael Goavec-Merou 728afdd758 build/efinix/common: DifferentialInput support 2023-10-02 17:32:49 +02:00
Gwenhael Goavec-Merou 73a28d2c04 build/efinix/ifacewriter: fix LVDS_TX, complete LVDS_RX 2023-10-02 17:32:08 +02:00
Gwenhael Goavec-Merou 97c84ebf27 build/efinix/common: adding DifferentialOutput support 2023-10-02 14:56:23 +02:00
Gwenhael Goavec-Merou cd1bd73a87 build/efinix/ifacewriter: adding method to generate lvds python code 2023-10-02 14:53:27 +02:00
Gwenhael Goavec-Merou 9842c95ef5 build/efinix/platform: adding method to get resource name based on signal 2023-10-02 14:45:10 +02:00
AndrewD e8689eb1dc
Merge pull request #1786 from motec-research/json2renode 
litex_json2renode: fix --bios-binary and add --opensbi-binary
 2023-09-30 12:41:58 +10:00
Florent Kermarrec f5b7c0d88e CHANGES: Update. 2023-09-26 13:49:19 +02:00
enjoy-digital eda2221a78
Merge pull request #1789 from protech-engineering/protech 
Add Debug support for NEORV32
 2023-09-26 13:45:35 +02:00
Matteo Marzaro a0f4c3715d Update NEORV32 to verion 1.8.9 2023-09-26 11:13:18 +02:00
Andrew Dennison 564f96c6c7 litex_json2renode: fix --bios-binary and add --opensbi-binary 
--bios-binary is reverted to loading the bios into _rom_ as per the documentation and litex defaults
--opensbi-binary is added to load the openSBI binary into the opensbi memory region

The examples documented in the wiki now work again
 2023-09-25 19:34:09 +10:00
Dolu1990 3d956af81d core/vexriscv_smp add --hardware-breakpoints INT to allow hardware breakpoint on PC 2023-09-20 09:10:20 +02:00
enjoy-digital 7d73873741
Merge pull request #1782 from enjoy-digital/ci-dev-test 
Switch CI to litex_setup.py --dev.
 2023-09-18 10:02:36 +02:00
Florent Kermarrec e0be028753 litex_setup: Don't do repo init in dev_mode (SSH clone) if running on CI. 2023-09-18 09:20:48 +02:00
Florent Kermarrec 04a33c5ddb CHANGES: Update. 2023-09-18 09:09:45 +02:00
enjoy-digital 4639c7b39c
Merge pull request #1776 from Dolu1990/nax-smp 
core/naxriscv provide a deployable NaxRiscv SMP
 2023-09-18 09:05:43 +02:00
Florent Kermarrec 8bd548d453 CHANGES.md: Start listing changes since 2023.08. 2023-09-18 09:02:05 +02:00
Florent Kermarrec 46d9d8c780 README: Update sponsors. 2023-09-18 09:02:00 +02:00
Florent Kermarrec b931499c12 build: Remove osfpga skeleton (would need feedbacks & updates). 2023-09-18 09:01:48 +02:00
enjoy-digital 351a583f1c
Merge pull request #1780 from timkpaine/tkp/version 
update version number to 2023.08
 2023-09-18 08:37:57 +02:00
Tim Paine 6162a6dc90 update version number to 2023.08 2023-09-17 17:42:53 -04:00
Florent Kermarrec de608ee114 ci: Switch install to --dev. 2023-09-17 21:59:55 +02:00
Giulio Girardi eb54ec7402 Add Debug support for NEORV32 2023-09-16 10:41:18 +00:00
enjoy-digital 639462ce46
Merge pull request #1778 from zeldin/issue_1777 
gen/fhdl/verilog: Fix #1777.
 2023-09-15 13:21:38 +02:00
Marcus Comstedt 6da1482336 gen/fhdl/verilog: Fix #1777. 2023-09-14 17:53:51 +02:00
Dolu1990 ff3318b20d
Update litex_setup.py with naxriscv smp 2023-09-14 11:25:02 +02:00
Florent Kermarrec a2c2c211c5 Changes.md: Release 2023.08. 2023-09-14 10:47:37 +02:00
Dolu1990 51592df260 debug 2023-09-14 07:19:05 +02:00
Dolu1990 e2c3a50e99 core/naxriscv allow memory less gen 2023-09-13 23:10:10 +02:00
Dolu1990 e8ed93c571 core/naxriscv git fix attempt 2023-09-13 20:41:27 +02:00
Dolu1990 2e4ebc8ec3 core/naxriscv git fix attempt 2023-09-13 19:42:16 +02:00
Dolu1990 b160507042 core/naxriscv add rvls git 2023-09-13 18:52:40 +02:00
Dolu1990 50b9f44d26 make naxriscv dma optional again 2023-09-13 16:23:39 +02:00
Dolu1990 d40d76fe4e fix indent 2023-09-13 16:18:44 +02:00
Dolu1990 5e0b8969ee Provide a deployable naxriscv SMP 2023-09-13 16:16:27 +02:00
Dolu1990 c16add73b4 core/vexriscv_smp add --expose-time, which add "clint_time" as output of the cpu. 2023-09-12 10:42:44 +02:00
Dolu1990 5d9dd1059d core/usb_ohci fix generation 2023-09-12 10:41:47 +02:00
Florent Kermarrec d165418719 CHANGES.md: Update. 2023-09-12 09:35:53 +02:00
Florent Kermarrec bcc7e56dc6 build/efinix/common: Add EfinixClkInput/Ouptut to use then in RGMII PHYs and avoid duplicating block code. 2023-09-12 09:30:45 +02:00
Florent Kermarrec 412f0f59b9 build/io: Add ClkInput/Ouptut to be able to abstract Clk Input/Output primitives. 2023-09-12 09:29:45 +02:00
Florent Kermarrec 36ce71d59b clock/efinix: Avoid manual n parameter and handle it internally. 2023-09-11 10:11:58 +02:00
Dolu1990 112f78bde3 cores/vexriscv_smp add risc-v official debug support via --with-privileged-debug 
Using https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/tcl/openocd/naxriscv_jtag_tunneled.tcl
 2023-09-08 16:42:09 +02:00
Florent Kermarrec 022bdf3cdc tools/litex_client: Add binary mode to read_memory and fix hex/binary prefix in dump_registers. 2023-09-08 16:12:04 +02:00
Florent Kermarrec 6c30cb8695 litex_setup.py: Use fixed sha1 version of Migen. 
Migen switched from setup.py to pyproject.toml, we'll need to handle this.
 2023-09-08 10:41:30 +02:00